參數(shù)資料
型號(hào)： M1A3P400-1FGG256II
元件分類(lèi)： FPGA
英文描述： FPGA, 9216 CLBS, 400000 GATES, 350 MHz, PBGA256
封裝： 17 X 17 MM, 1.60 MM HEIGHT, 1 MM PITCH, GREEN, FBGA-256
文件頁(yè)數(shù)： 49/49頁(yè)
文件大?。?/td> 5893K
代理商： M1A3P400-1FGG256II
ProASIC3 DC and Switching Characteristics
2- 82
v1.3
Table 2-104 A3P600 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
Description
–2
–1
Std.
–F
Units
Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 Min.1 Max.2
tRCKL
Input LOW Delay for Global Clock
0.87 1.09 0.99 1.24 1.17 1.46 1.40 1.75
ns
tRCKH
Input HIGH Delay for Global Clock
0.861.11 0.981.271.151.491.381.79
ns
tRCKMPWH Minimum Pulse Width HIGH for Global Clock
ns
tRCKMPWL Minimum Pulse Width LOW for Global Clock
ns
tRCKSW
Maximum Skew for Global Clock
0.26
0.29
0.34
0.41
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Table 2-105 A3P1000 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
Description
–2
–1
Std.
–F
Units
Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 Min.1 Max.2
tRCKL
Input LOW Delay for Global Clock
0.94 1.16 1.07 1.32 1.26 1.55 1.51 1.86
ns
tRCKH
Input HIGH Delay for Global Clock
0.931.19 1.061.351.241.591.491.91
ns
tRCKMPWH Minimum Pulse Width HIGH for Global Clock
ns
tRCKMPWL Minimum Pulse Width LOW for Global Clock
ns
tRCKSW
Maximum Skew for Global Clock
0.26
0.29
0.35
0.41
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M1A3P400-1FGG484 功能描述:IC FPGA 1KB FLASH 400K 484-FBGA RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:ProASIC3 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門(mén)數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17）
M1A3P400-1FGG484I 功能描述:IC FPGA 1KB FLASH 400K 484-FBGA RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:ProASIC3 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門(mén)數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17）
M1A3P400-1PQ144 制造商:ACTEL 制造商全稱(chēng):Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs
M1A3P400-1PQ144ES 制造商:ACTEL 制造商全稱(chēng):Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs
M1A3P400-1PQ144I 制造商:ACTEL 制造商全稱(chēng):Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs
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