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參數(shù)資料
| 型號(hào)： | M1A3P400-1PQ208II |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 9216 CLBS, 400000 GATES, 350 MHz, PQFP208 |
| 封裝： | 28 X 28 MM, 3.40 MM HEIGHT, 0.50 MM PITCH, PLASTIC, QFP-208 |
| 文件頁數(shù)： | 28/49頁 |
| 文件大?。?/td> | 5893K |
| 代理商： | M1A3P400-1PQ208II |
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ProASIC3 DC and Switching Characteristics
v1.3
2 - 107
Advance v0.5
(continued)
The "I/O Banks" section is new. This section explains the following types of I/Os:
Advanced
Standard+
Standard
Table 2-12 Automotive ProASIC3 Bank Types Definition and Differences is
new. This table describes the standards listed above.
2-29
PCI-X 3.3 V was added to the Compatible Standards for 3.3 V in Table 2-
11 VCCI Voltages and Compatible Standards
2-29
Table 2-13 ProASIC3 I/O Features was updated.
2-30
The "Double Data Rate (DDR) Support" section was updated to include
information concerning implementation of the feature.
2-32
The "Electrostatic Discharge (ESD) Protection" section was updated to include
testing information.
2-35
Level 3 and 4 descriptions were updated in Table 2-43 I/O Hot-Swap and 5 V
Input Tolerance Capabilities in ProASIC3 Devices.
2-64
The notes in Table 2-43 I/O Hot-Swap and 5 V Input Tolerance Capabilities in
ProASIC3 Devices were updated.
2-64
The "Simultaneous Switching Outputs (SSOs) and Printed Circuit Board Layout"
section is new.
2-41
A footnote was added to Table 2-14 Maximum I/O Frequency for Single-Ended
and Differential I/Os in All Banks in Automotive ProASIC3 Devices (maximum
drive strength and high slew selected).
2-30
Table 2-18 Automotive ProASIC3 I/O Attributes vs. I/O Standard Applications
2-45
Table 2-50 ProASIC3 Output Drive (OUT_DRIVE) for Standard I/O Bank Type
(A3P030 device)
2-83
Table 2-51 ProASIC3 Output Drive for Standard+ I/O Bank Type was updated.
2-84
Table 2-54 ProASIC3 Output Drive for Advanced I/O Bank Type was updated.
2-84
The "x" was updated in the "User I/O Naming Convention" section.
2-48
The "VCC Core Supply Voltage" pin description was updated.
2-50
The "VMVx I/O Supply Voltage (quiet)" pin description was updated to include
information concerning leaving the pin unconnected.
2-50
The "VJTAG JTAG Supply Voltage" pin description was updated.
2-50
The "VPUMP Programming Supply Voltage" pin description was updated to
include information on what happens when the pin is tied to ground.
2-50
The "I/O User Input/Output" pin description was updated to include information
on what happens when the pin is unused.
2-50
The "JTAG Pins" section was updated to include information on what happens
when the pin is unused.
2-51
The "Programming" section was updated to include information concerning
serialization.
2-53
The
"JTAG
1532"
section
was
updated
to
include
SAMPLE/PRELOAD
information.
2-54
"DC and Switching Characteristics" chapter was updated with new information.
3-1
Previous Version
Changes in Current Version (v1.3)
Page
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M1A3P400-1PQG208II | FPGA, 9216 CLBS, 400000 GATES, 350 MHz, PQFP208 |
| M1A3P400-2FG144II | FPGA, 9216 CLBS, 400000 GATES, 350 MHz, PBGA144 |
| M1A3P400-2FG256II | FPGA, 9216 CLBS, 400000 GATES, 350 MHz, PBGA256 |
| M1A3P400-2FG484II | FPGA, 9216 CLBS, 400000 GATES, 350 MHz, PBGA484 |
| M1A3P400-2FGG144II | FPGA, 9216 CLBS, 400000 GATES, 350 MHz, PBGA144 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M1A3P400-1PQG144 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs |
| M1A3P400-1PQG144ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs |
| M1A3P400-1PQG144I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs |
| M1A3P400-1PQG144PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs |
| M1A3P400-1PQG208 | 功能描述:IC FPGA 1KB FLASH 400K 208-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASIC3 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14） |
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