參數(shù)資料
型號(hào): M1A3P400-2FG484II
元件分類: FPGA
英文描述: FPGA, 9216 CLBS, 400000 GATES, 350 MHz, PBGA484
封裝: 23 X 23 MM, 2.23 MM HEIGHT, 1 MM PITCH, FBGA-484
文件頁(yè)數(shù): 17/49頁(yè)
文件大小: 5893K
代理商: M1A3P400-2FG484II
ProASIC3 DC and Switching Characteristics
v1.3
2 - 97
Table 2-110 FIFO (for A3P250 only, aspect-ratio-dependent)
Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
Description
–2
–1
Std.
–F
Units
tENS
REN_B, WEN_B Setup Time
3.26
3.71
4.36
5.24
ns
tENH
REN_B, WEN_B Hold Time
0.00
ns
tBKS
BLK_B Setup Time
0.19
0.22
0.26
0.31
ns
tBKH
BLK_B Hold Time
0.00
ns
tDS
Input Data (DI) Setup Time
0.18
0.21
0.25
0.29
ns
tDH
Input Data (DI) Hold Time
0.00
ns
tCKQ1
Clock HIGH to New Data Valid on DO (flow-through)
2.17
2.47
2.90
3.48
ns
tCKQ2
Clock HIGH to New Data Valid on DO (pipelined)
0.94
1.07
1.26
1.52
ns
tRCKEF
RCLK HIGH to Empty Flag Valid
1.72
1.96
2.30
2.76
ns
tWCKFF
WCLK HIGH to Full Flag Valid
1.63
1.86
2.18
2.62
ns
tCKAF
Clock HIGH to Almost Empty/Full Flag Valid
6.19
7.05
8.29
9.96
ns
tRSTFG
RESET_B LOW to Empty/Full Flag Valid
1.69
1.93
2.27
2.72
ns
tRSTAF
RESET_B LOW to Almost Empty/Full Flag Valid
6.13
6.98
8.20
9.85
ns
tRSTBQ
RESET_B LOW to Data Out LOW on DO (flow-through)
0.921.051.231.48
ns
RESET_B LOW to Data Out LOW on DO (pipelined)
0.92
1.05
1.23
1.48
ns
tREMRSTB
RESET_B Removal
0.29
0.33
0.38
0.46
ns
tRECRSTB
RESET_B Recovery
1.50
1.71
2.01
2.41
ns
tMPWRSTB
RESET_B Minimum Pulse Width
0.21
0.24
0.29
0.34
ns
tCYC
Clock Cycle Time
3.23
3.68
4.32
5.19
ns
FMAX
Maximum Frequency for FIFO
310
272
231
193
MHz
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