參數(shù)資料
型號: M1A3P400-FFG144
元件分類: FPGA
英文描述: FPGA, 9216 CLBS, 400000 GATES, 350 MHz, PBGA144
封裝: 13X 13 MM, 1.45 MM HEIGHT, 1 MM PITCH, FBGA-144
文件頁數(shù): 24/49頁
文件大?。?/td> 5893K
代理商: M1A3P400-FFG144
ProASIC3 DC and Switching Characteristics
v1.3
2 - 103
JTAG 1532 Characteristics
JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays
to the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O
Timing Characteristics
Table 2-116 JTAG 1532
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
–2
–1
Std.
Units
tDISU
Test Data Input Setup Time
0.50
0.57
0.67
ns
tDIHD
Test Data Input Hold Time
1.00
1.13
1.33
ns
tTMSSU
Test Mode Select Setup Time
0.50
0.57
0.67
ns
tTMDHD
Test Mode Select Hold Time
1.00
1.13
1.33
ns
tTCK2Q
Clock to Q (data out)
6.00
6.80
8.00
ns
tRSTB2Q
Reset to Q (data out)
20.00
22.67
26.67
ns
FTCKMAX
TCK Maximum Frequency
25.00
22.00
19.00
MHz
tTRSTREM
ResetB Removal Time
0.00
ns
tTRSTREC
ResetB Recovery Time
0.20
0.23
0.27
ns
tTRSTMPW
ResetB Minimum Pulse
TBD
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6
for derating values.
相關PDF資料
PDF描述
M1A3P400-FFG256 FPGA, 9216 CLBS, 400000 GATES, 350 MHz, PBGA256
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