參數(shù)資料
型號： M1A3P400-FG484II
元件分類： FPGA
英文描述： FPGA, 9216 CLBS, 400000 GATES, 350 MHz, PBGA484
封裝： 23 X 23 MM, 2.23 MM HEIGHT, 1 MM PITCH, FBGA-484
文件頁數(shù)： 47/49頁
文件大?。?/td> 5893K
代理商： M1A3P400-FG484II
ProASIC3 DC and Switching Characteristics
2- 80
v1.3
Table 2-100 A3P060 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
Description
–2
–1
Std.
–F
Units
Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 Min.1 Max.2
tRCKL
Input LOW Delay for Global Clock
0.71 0.93 0.81 1.05 0.95 1.24 1.14 1.49
ns
tRCKH
Input HIGH Delay for Global Clock
0.700.96 0.801.090.941.281.131.54
ns
tRCKMPWH Minimum Pulse Width HIGH for Global Clock
ns
tRCKMPWL Minimum Pulse Width LOW for Global Clock
ns
tRCKSW
Maximum Skew for Global Clock
0.26
0.29
0.34
0.41
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Table 2-101 A3P125 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
Description
–2
–1
Std.
–F
Units
Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 Min.1 Max.2
tRCKL
Input LOW Delay for Global Clock
0.77 0.99 0.87 1.12 1.03 1.32 1.24 1.58
ns
tRCKH
Input HIGH Delay for Global Clock
0.761.02 0.871.161.021.371.231.64
ns
tRCKMPWH Minimum Pulse Width HIGH for Global Clock
ns
tRCKMPWL Minimum Pulse Width LOW for Global Clock
ns
tRCKSW
Maximum Skew for Global Clock
0.26
0.29
0.34
0.41
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
相關PDF資料
PDF描述
M1A3P400-FGG144II FPGA, 9216 CLBS, 400000 GATES, 350 MHz, PBGA144
M1A3P400-FGG256II FPGA, 9216 CLBS, 400000 GATES, 350 MHz, PBGA256
M1A3P400-FGG484II FPGA, 9216 CLBS, 400000 GATES, 350 MHz, PBGA484
M1A3P400-FPQ208 FPGA, 9216 CLBS, 400000 GATES, 350 MHz, PQFP208
M1A3P400-FPQG208 FPGA, 9216 CLBS, 400000 GATES, 350 MHz, PQFP208
相關代理商/技術參數(shù)
參數(shù)描述
M1A3P400-FGG144 功能描述:IC FPGA 1KB FLASH 400K 144-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASIC3 標準包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計:- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應商設備封裝:289-CSP（14x14）
M1A3P400-FGG144ES 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs
M1A3P400-FGG144I 功能描述:IC FPGA 1KB FLASH 400K 144-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASIC3 標準包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應商設備封裝:256-FPBGA（17x17）
M1A3P400-FGG144PP 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs
M1A3P400-FGG256 功能描述:IC FPGA 1KB FLASH 400K 256-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASIC3 標準包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計:- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應商設備封裝:289-CSP（14x14）
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