ARM CortexTM-M1 2P ro d u c t B r " />
參數(shù)資料
型號(hào): M1A3P600-1FGG484I
廠商: Microsemi SoC
文件頁(yè)數(shù): 5/12頁(yè)
文件大小: 0K
描述: IC FPGA 1KB FLASH 600K 484-FBGA
標(biāo)準(zhǔn)包裝: 40
系列: ProASIC3
RAM 位總計(jì): 110592
輸入/輸出數(shù): 235
門數(shù): 600000
電源電壓: 1.425 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 484-BGA
供應(yīng)商設(shè)備封裝: 484-FPBGA(23x23)
ARM CortexTM-M1
2P ro d u c t B r i e f
Figure 1 shows an ARM Cortex-M1 processor with debug block diagram.
The NVIC is closely coupled to the ARM Cortex-M1 core
to achieve low-latency interrupt processing. The versions
currently available for use in M1 devices support 1
interrupt with 4 levels of priority. Future versions will
support up to 32 interrupts. To simplify software
development, the processor state is automatically saved
on interrupt entry, and restored on interrupt exist, with
no instruction overhead.
The ARM Cortex-M1 Thumb instruction set’s 16-bit
instruction length allows it to approach twice the density
in memory of standard 32-bit ARM code while retaining
most of the ARM performance advantage over a
traditional 16-bit processor using 16-bit registers. This is
possible because Thumb code operates on the 32-bit
register set in the processor. Thumb code is able to
provide up to 65% of the code size of ARM, and 160% of
the performance of an equivalent ARM processor
connected to a 16-bit memory system.
Figure 1 Processor with Debug Block Diagram
Processor with Debug
AHB-PPB
NVIC
Debug Subsystem
AHB Decoder
AHB Multiplexer
AHB Matrix
Debug ITCM Interface
Debug DTCM Interface
Breakpoint Unit
Data Watchpoint Unit
Debug Control
ROM Table
Internal PPB Signals
External Bus Signals
DAP
AHB-AP
SWJ-DP
Memory Interface
ITCM
DTCM
Core
Dbg
AHB Master
NVIC Interrupt Interface External Interface
Debug Port
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