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參數(shù)資料
| 型號(hào)： | M1A3P600-1FGG484I |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 13824 CLBS, 600000 GATES, PBGA484 |
| 封裝： | 23 X 23 MM, 2.23 MM HEIGHT, 1 MM PITCH, GREEN, FBGA-484 |
| 文件頁(yè)數(shù)： | 175/218頁(yè) |
| 文件大?。?/td> | 6270K |
| 代理商： | M1A3P600-1FGG484I |
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ProASIC3 Device Family Overview
1- 2
v1.3
Security, built into the FPGA fabric, is an inherent component of the ProASIC3 family. The flash cells
are located beneath seven metal layers, and many device design and layout techniques have been
used to make invasive attacks extremely difficult. The ProASIC3 family, with FlashLock and AES
security, is unique in being highly resistant to both invasive and noninvasive attacks. Your valuable
IP is protected and secure, making remote ISP possible. A ProASIC3 device provides the most
impenetrable security for programmable logic designs.
Single Chip
Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed,
the configuration data is an inherent part of the FPGA structure, and no external configuration
data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based
ProASIC3 FPGAs do not require system configuration components such as EEPROMs or
microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB
area, and increases security and system reliability.
Live at Power-Up
The Actel flash-based ProASIC3 devices support Level 0 of the LAPU classification standard. This
feature helps in system component initialization, execution of critical tasks before the processor
wakes up, setup and configuration of memory blocks, clock generation, and bus activity
management. The LAPU feature of flash-based ProASIC3 devices greatly simplifies total system
design and reduces total system cost, often eliminating the need for CPLDs and clock generation
PLLs that are used for these purposes in a system. In addition, glitches and brownouts in system
power will not corrupt the ProASIC3 device's flash configuration, and unlike SRAM-based FPGAs,
the device will not have to be reloaded when system power is restored. This enables the reduction
or complete removal of the configuration PROM, expensive voltage monitor, brownout detection,
and clock generator devices from the PCB design. Flash-based ProASIC3 devices simplify total
system design and reduce cost and design risk while increasing system reliability and improving
system initialization time.
Firm Errors
Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere,
strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the
configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way.
These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be
a complete system failure. Firm errors do not exist in the configuration memory of ProASIC3 flash-
based FPGAs. Once it is programmed, the flash cell configuration element of ProASIC3 FPGAs
cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft)
errors occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error
detection and correction (EDAC) circuitry built into the FPGA fabric.
Low Power
Flash-based ProASIC3 devices exhibit power characteristics similar to an ASIC, making them an ideal
choice for power-sensitive applications. ProASIC3 devices have only a very limited power-on current
surge and no high-current transition period, both of which occur on many FPGAs.
ProASIC3 devices also have low dynamic power consumption to further maximize power savings.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M1A3P600-1FGG484 | FPGA, 13824 CLBS, 600000 GATES, 350 MHz, PBGA484 |
| M1A3P600-1PQ208I | FPGA, 13824 CLBS, 600000 GATES, PQFP208 |
| M1A3P600-1PQ208 | FPGA, 13824 CLBS, 600000 GATES, 350 MHz, PQFP208 |
| M1A3P600-1PQG208I | FPGA, 13824 CLBS, 600000 GATES, PQFP208 |
| M1A3P600-1PQG208 | FPGA, 13824 CLBS, 600000 GATES, 350 MHz, PQFP208 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M1A3P600-1PQ144 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs |
| M1A3P600-1PQ144ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs |
| M1A3P600-1PQ144I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs |
| M1A3P600-1PQ144PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs |
| M1A3P600-1PQ208 | 功能描述:IC FPGA 1KB FLASH 600K 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASIC3 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17） |
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