Revision 13 2-53 Table 2-84 Parameter Definition and Measuring Nodes Parameter Name Parameter Definition Meas" />
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  • 參數(shù)資料
    型號(hào): M1A3PE3000-1FGG484
    廠商: Microsemi SoC
    文件頁數(shù): 127/162頁
    文件大小: 0K
    描述: IC FPGA 1KB FLASH 3M 484-FBGA
    標(biāo)準(zhǔn)包裝: 40
    系列: ProASIC3E
    RAM 位總計(jì): 516096
    輸入/輸出數(shù): 341
    門數(shù): 3000000
    電源電壓: 1.425 V ~ 1.575 V
    安裝類型: 表面貼裝
    工作溫度: 0°C ~ 70°C
    封裝/外殼: 484-BGA
    供應(yīng)商設(shè)備封裝: 484-FPBGA(23x23)
    ProASIC3E Flash Family FPGAs
    Revision 13
    2-53
    Table 2-84 Parameter Definition and Measuring Nodes
    Parameter Name
    Parameter Definition
    Measuring Nodes
    (from, to)*
    tOCLKQ
    Clock-to-Q of the Output Data Register
    H, DOUT
    tOSUD
    Data Setup Time for the Output Data Register
    F, H
    tOHD
    Data Hold Time for the Output Data Register
    F, H
    tOSUE
    Enable Setup Time for the Output Data Register
    G, H
    tOHE
    Enable Hold Time for the Output Data Register
    G, H
    tOPRE2Q
    Asynchronous Preset-to-Q of the Output Data Register
    L, DOUT
    tOREMPRE
    Asynchronous Preset Removal Time for the Output Data Register
    L, H
    tORECPRE
    Asynchronous Preset Recovery Time for the Output Data Register
    L, H
    tOECLKQ
    Clock-to-Q of the Output Enable Register
    H, EOUT
    tOESUD
    Data Setup Time for the Output Enable Register
    J, H
    tOEHD
    Data Hold Time for the Output Enable Register
    J, H
    tOESUE
    Enable Setup Time for the Output Enable Register
    K, H
    tOEHE
    Enable Hold Time for the Output Enable Register
    K, H
    tOEPRE2Q
    Asynchronous Preset-to-Q of the Output Enable Register
    I, EOUT
    tOEREMPRE
    Asynchronous Preset Removal Time for the Output Enable Register
    I, H
    tOERECPRE
    Asynchronous Preset Recovery Time for the Output Enable Register
    I, H
    tICLKQ
    Clock-to-Q of the Input Data Register
    A, E
    tISUD
    Data Setup Time for the Input Data Register
    C, A
    tIHD
    Data Hold Time for the Input Data Register
    C, A
    tISUE
    Enable Setup Time for the Input Data Register
    B, A
    tIHE
    Enable Hold Time for the Input Data Register
    B, A
    tIPRE2Q
    Asynchronous Preset-to-Q of the Input Data Register
    D, E
    tIREMPRE
    Asynchronous Preset Removal Time for the Input Data Register
    D, A
    tIRECPRE
    Asynchronous Preset Recovery Time for the Input Data Register
    D, A
    Note: *See Figure 2-25 on page 2-52 for more information.
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