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參數(shù)資料
| 型號： | M1A3PE3000L-1FGG484I |
| 廠商： | Microsemi SoC |
| 文件頁數(shù)： | 65/162頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 1KB FLASH 3M 484-FBGA |
| 標準包裝： | 40 |
| 系列： | ProASIC3EL |
| RAM 位總計： | 516096 |
| 輸入/輸出數(shù)： | 341 |
| 門數(shù)： | 3000000 |
| 電源電壓： | 1.14V ~ 1.575 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 484-BGA |
| 供應商設備封裝： | 484-FPBGA（23x23） |
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ProASIC3E Flash Family FPGAs
Revision 13
5-7
v2.0
(continued)
Table 3-6 Temperature and Voltage Derating Factors for Timing Delays was
updated.
3-5
Table 3-5 Package Thermal Resistivities was updated.
3-5
Table 3-10 Different Components Contributing to the Dynamic Power
Consumption in ProASIC3E Devices was updated.
3-8
tWRO and tCCKH were added to Table 3-94 RAM4K9 and Table
3-95 RAM512X18.
3-74 to
3-74
The note in Table 3-24 I/O Input Rise Time, Fall Time, and Related I/O
Reliability was updated.
3-23
Figure 3-43 Write Access After Write onto Same Address, Figure 3-44 Read
Access After Write onto Same Address, and Figure 3-45 Write Access After
Read onto Same Address are new.
3-71 to 3-
73
Figure 3-53 Timing Diagram was updated.
3-80
Notes were added to the package diagrams identifying if they were top or bottom
view.
N/A
The A3PE1500 "208-Pin PQFP" table is new.
4-4
The A3PE1500 "484-Pin FBGA" table is new.
4-18
The A3PE1500 "A3PE1500 Function" table is new.
4-24
Advance v0.6
(January 2007)
In the "Packaging Tables" table, the number of I/Os for the A3PE1500 was
changed for the FG484 and FG676 packages.
ii
Advance v0.5
(April 2006)
B-LVDS and M-LDVS are new I/O standards added to the datasheet.
N/A
The term flow-through was changed to pass-through.
N/A
Figure 2-8 Very-Long-Line Resources was updated.
2-8
The footnotes in Figure 2-27 CCC/PLL Macro were updated.
2-28
The Delay Increments in the Programmable Delay Blocks specification in Figure
2-24 ProASIC3E CCC Options.
2-24
The "SRAM and FIFO" section was updated.
2-21
The "RESET" section was updated.
2-25
The "WCLK and RCLK" section was updated.
2-25
The "RESET" section was updated.
2-25
The "RESET" section was updated.
2-27
B-LVDS and M-LDVS are new I/O standards added to the datasheet.
N/A
The term flow-through was changed to pass-through.
N/A
Figure 2-8 Very-Long-Line Resources was updated.
2-8
The footnotes in Figure 2-27 CCC/PLL Macro were updated.
2-28
The Delay Increments in the Programmable Delay Blocks specification in Figure
2-24 ProASIC3E CCC Options.
2-24
The "SRAM and FIFO" section was updated.
2-21
The "RESET" section was updated.
2-25
The "WCLK and RCLK" section was updated.
2-25
Revision
Changes
Page
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M1A3PE3000L-1FGG484M | 制造商:Microsemi Corporation 功能描述:FPGA ProASIC?3EL Family 3M Gates 130nm Technology 1.2V/1.5V 484-Pin FBGA 制造商:Microsemi Corporation 功能描述:FPGA PROASIC?3EL FAMILY 3M GATES 130NM (CMOS) TECHNOLOGY 1.2 - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 3M GATES W/M1 484FBGA 制造商:Microsemi Corporation 功能描述:IC FPGA 341 I/O 484FBGA |
| M1A3PE3000L-1FGG896 | 功能描述:IC FPGA 1KB FLASH 3M 896-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASIC3EL 產(chǎn)品培訓模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應商設備封裝:484-FBGA（23x23） |
| M1A3PE3000L-1FGG896I | 功能描述:IC FPGA 1KB FLASH 3M 896-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASIC3EL 標準包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應商設備封裝:352-CQFP（75x75） |
| M1A3PE3000L-1FGG896M | 制造商:Microsemi Corporation 功能描述:FPGA PROASIC?3EL FAMILY 3M GATES 130NM (CMOS) TECHNOLOGY 1.2 - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 3M GATES W/M1 896FBGA 制造商:Microsemi Corporation 功能描述:IC FPGA 620 I/O 896FBGA |
| M1A3PE3000L-1PQ144M | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Military ProASIC3/EL Low-Power Flash FPGAs |
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