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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� M1AFS1500-2FG676I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 276/334闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA 8MB FLASH 1.5M 676-FBGA
妯欐簴鍖呰锛� 40
绯诲垪锛� Fusion®
RAM 浣嶇附瑷堬細 276480
杓稿叆/杓稿嚭鏁�(sh霉)锛� 252
闁€鏁�(sh霉)锛� 1500000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 100°C
灏佽/澶栨锛� 676-BGA
渚涙噳鍟嗚ō鍌欏皝瑁濓細 676-FBGA锛�27x27锛�
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Device Architecture
2-30
Revision 4
CCC and PLL Characteristics
Timing Characteristics
Table 2-12 Fusion CCC/PLL Specification
Parameter
Min.
Typ.
Max.
Unit
Clock Conditioning Circuitry Input Frequency fIN_CCC
1.5
350
MHz
Clock Conditioning Circuitry Output Frequency fOUT_CCC
0.75
350
MHz
Delay Increments in Programmable Delay Blocks1, 2
1603
ps
Number of Programmable Values in Each Programmable
Delay Block
32
Input Period Jitter
1.5
ns
CCC Output Peak-to-Peak Period Jitter FCCC_OUT
Max Peak-to-Peak Period Jitter
1 Global
Network
Used
3 Global
Networks
Used
0.75 MHz to 24 MHz
1.00%
24 MHz to 100 MHz
1.50%
100 MHz to 250 MHz
2.25%
250 MHz to 350 MHz
3.50%
Acquisition Time
LockControl = 0
300
s
LockControl = 1
6.0
ms
Tracking Jitter4
LockControl = 0
1.6
ns
LockControl = 1
0.8
ns
Output Duty Cycle
48.5
51.5
%
Delay Range in Block: Programmable Delay 1 1, 2
0.6
5.56
ns
Delay Range in Block: Programmable Delay 2 1, 2
0.025
5.56
ns
Delay Range in Block: Fixed Delay 1, 2
2.2
ns
Notes:
1. This delay is a function of voltage and temperature. See Table 3-7 on page 3-9 for deratings.
2. TJ = 25掳C, VCC = 1.5 V
3. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay
increments are available. Refer to the Libero SoC Online Help associated with the core for more information.
4. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input clock edge.
Tracking jitter does not measure the variation in PLL output period, which is covered by period jitter parameter.
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