Fusion Family of Mixed Signal FPGAs
Revision 4
2-211
SSTL3 Class II
Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). Fusion devices support Class
II. This provides a differential amplifier input buffer and a push-pull output buffer.
Timing Characteristics
Table 2-165 Minimum and Maximum DC Input and Output Levels
SSTL3 Class II
VIL
VIH
VOL
VOH
IOL IOH IOSL
IOSH
IIL1 IIH2
Drive Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
VmA mA
Max.
mA3
Max.
mA3
A4 A4
21 mA
–0.3 VREF – 0.2 VREF + 0.2
3.6
0.5
VCCI – 0.9 21
21
109
103
10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
Figure 2-133 AC Loading
Table 2-166 AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
VREF (typ.) (V)
VTT (typ.) (V)
CLOAD (pF)
VREF – 0.2
VREF + 0.2
1.5
1.485
30
Test Point
30 pF
25
SSTL3
Class II
VTT
Table 2-167 SSTL3- Class II
Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 3.0 V, VREF = 1.5 V
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
Std.
0.66
2.07
0.04
1.25
0.43
2.10
1.67
4.34
3.91
ns
–1
0.56
1.76
0.04
1.06
0.36
1.79
1.42
3.69
3.32
ns
–2
0.49
1.54
0.03
0.93
0.32
1.57
1.25
3.24
2.92
ns
Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on