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參數(shù)資料
| 型號(hào)： | M1AFS250-FPQG208 |
| 元件分類(lèi)： | FPGA |
| 英文描述： | FPGA, 250000 GATES, PQFP208 |
| 封裝： | 0.50 MM PITCH, GREEN, PQFP-208 |
| 文件頁(yè)數(shù)： | 156/318頁(yè) |
| 文件大?。?/td> | 10129K |
| 代理商： | M1AFS250-FPQG208 |
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Actel Fusion Mixed-Signal FPGAs
Pr el iminar y v1 .7
2- 223
Actel Designer software is a place-and-route tool and provides a comprehensive suite of backend
support tools for FPGA development. The Designer software includes the following:
SmartTime – a world-class integrated static timing analyzer and constraints editor that
supports timing-driven place-and-route
NetlistViewer – a design netlist schematic viewer
ChipPlanner – a graphical floorplanning viewer and editor
SmartPower – a sophisticated power analysis environment that gives designers the ability to
quickly determine the power consumption of an FPGA or its components
PinEditor – a graphical application for editing pin assignments and I/O attributes
I/O Attribute Editor – displays all assigned and unassigned I/O macros and their attributes in
a spreadsheet format
With the Designer software, a user can lock the design pins before layout while minimally
impacting the results of place-and-route. Additionally, the Actel back-annotation flow is
compatible with all major simulators. Included in the Designer software is SmartGen core
generator, which easily creates commonly used logic functions for implementation into your
Fusion-based schematic or HDL design.
Actel Designer software is compatible with the most popular FPGA design entry and verification
tools from EDA vendors, such as Cadence, Magma, Mentor Graphics, Synopsys, and Synplicity.
The Designer software is available for both the Windows and UNIX operating systems.
CoreMP7 and Cortex-M1 Software Tools
CoreConsole is the Intellectual Property Deployment Platform (IDP) that assists the developer in
programming the soft ARM core onto M7 (CoreMP7) and M1 (Cortex-M1) Fusion devices.
CoreConsole provides the seamless environment to work with the Libero IDE and Designer FPGA
development software tools concurrently.
Security
Fusion devices have a built-in 128-bit AES decryption core. The decryption core facilitates secure, in-
system programming of the FPGA core array fabric and the FlashROM. The FlashROM and the FPGA
core fabric can be programmed independently from each other, allowing the FlashROM to be
updated without the need for change to the FPGA core fabric. The AES master key is stored in on-
chip nonvolatile memory (flash). The AES master key can be preloaded into parts in a secure
programming environment (such as the Actel in-house programming center), and then "blank"
parts can be shipped to an untrusted programming or manufacturing center for final
personalization with an AES-encrypted bitstream. Late stage product changes or personalization
can be implemented easily and securely by simply sending a STAPL file with AES-encrypted data.
Secure remote field updates over public networks (such as the Internet) are possible by sending and
programming a STAPL file with AES-encrypted data. For more information, refer to the Fusion
Security application note.
128-Bit AES Decryption
The 128-bit AES standard (FIPS-192) block cipher is the National Institute of Standards and
Technology (NIST) replacement for DES (Data Encryption Standard FIPS46-2). AES has been
designed to protect sensitive government information well into the 21st century. It replaces the
aging DES, which NIST adopted in 1977 as a Federal Information Processing Standard used by
federal agencies to protect sensitive, unclassified information. The 128-bit AES standard has
3.4 × 1038 possible 128-bit key variants, and it has been estimated that it would take 1,000 trillion
years to crack 128-bit AES cipher text using exhaustive techniques. Keys are stored (securely) in
Fusion devices in nonvolatile flash memory. All programming files sent to the device can be
authenticated by the part prior to programming to ensure that bad programming data is not
loaded into the part that may possibly damage it. All programming verification is performed on-
chip, ensuring that the contents of Fusion devices remain secure.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M1AFS250-FQN180 | FPGA, 250000 GATES, PBCC180 |
| M1AFS250-FQNG180 | FPGA, 250000 GATES, PBCC180 |
| M20-1051700 | 34 CONTACT(S), FEMALE, TWO PART BOARD CONNECTOR, CRIMP, SOCKET |
| M20-1051800 | 36 CONTACT(S), FEMALE, TWO PART BOARD CONNECTOR, CRIMP, SOCKET |
| M20-1052400 | 48 CONTACT(S), FEMALE, TWO PART BOARD CONNECTOR, CRIMP, SOCKET |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M1AFS250-FPQG256ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
| M1AFS250-FPQG256I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
| M1AFS250-FPQG256PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
| M1AFS250-FQN256ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
| M1AFS250-FQN256I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
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