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參數(shù)資料
| 型號： | M1AFS600-1PQ208I |
| 廠商： | Microsemi SoC |
| 文件頁數(shù)： | 21/334頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA 4MB FLASH 600K 208-PQFP |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | Fusion® |
| RAM 位總計(jì)： | 110592 |
| 輸入/輸出數(shù)： | 95 |
| 門數(shù)： | 600000 |
| 電源電壓： | 1.425 V ~ 1.575 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 208-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 208-PQFP（28x28） |
Fusion Family of Mixed Signal FPGAs
Revision 4
2-101
There are several popular ADC architectures, each with advantages and limitations. The analog-to-digital
converter in Fusion devices is a switched-capacitor Successive Approximation Register (SAR) ADC. It
supports 8-, 10-, and 12-bit modes of operation with a cumulative sample rate up to 600 k samples per
second (ksps). Built-in bandgap circuitry offers 1% internal voltage reference accuracy or an external
reference voltage can be used.
As shown in Figure 2-81, a SAR ADC contains N capacitors with binary-weighted values.
To begin a conversion, all of the capacitors are quickly discharged. Then VIN is applied to all the
capacitors for a period of time (acquisition time) during which the capacitors are charged to a value very
close to VIN. Then all of the capacitors are switched to ground, and thus –VIN is applied across the
comparator. Now the conversion process begins. First, C is switched to VREF. Because of the binary
weighting of the capacitors, the voltage at the input of the comparator is then shown by EQ 11.
Voltage at input of comparator = –VIN + VREF / 2
EQ 11
If VIN is greater than VREF / 2, the output of the comparator is 1; otherwise, the comparator output is 0.
A register is clocked to retain this value as the MSB of the result. Next, if the MSB is 0, C is switched
back to ground; otherwise, it remains connected to VREF, and C / 2 is connected to VREF. The result at
the comparator input is now either –VIN + VREF / 4 or –VIN + 3 VREF / 4 (depending on the state of the
MSB), and the comparator output now indicates the value of the next most significant bit. This bit is
likewise registered, and the process continues for each subsequent bit until a conversion is completed.
The conversion process requires some acquisition time plus N + 1 ADC clock cycles to complete.
Figure 2-81 Example SAR ADC Architecture
Comparator
C
C / 2
C / 4
C / 2N–2
C / 2N–1
VREF
VIN
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AFS600-1PQ208I | IC FPGA 4MB FLASH 600K 208PQFP |
| AFS600-FG484I | IC FPGA 4MB FLASH 600K 484FBGA |
| M1AFS600-FG484I | IC FPGA 4MB FLASH 600K 484-FBGA |
| ASM43DSES | CONN EDGECARD 86POS .156 EYELET |
| ASM43DRTS | CONN EDGECARD 86POS DIP .156 SLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M1AFS600-1PQ256ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
| M1AFS600-1PQ256I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
| M1AFS600-1PQ256PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
| M1AFS600-1PQG208 | 功能描述:IC FPGA 4MB FLASH 600K 208-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Fusion® 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
| M1AFS600-1PQG208I | 功能描述:IC FPGA 4MB FLASH 600K 208-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Fusion® 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
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