1-8 Revision 23 Each I/O module contains several input, output, and enable registers. These registers allow the imple" />
參數(shù)資料
型號(hào): M1AGL600V2-CS281I
廠商: Microsemi SoC
文件頁(yè)數(shù): 46/250頁(yè)
文件大小: 0K
描述: IC FPGA 1KB FLASH 600K 281-CSP
標(biāo)準(zhǔn)包裝: 184
系列: IGLOO
邏輯元件/單元數(shù): 13824
RAM 位總計(jì): 110592
輸入/輸出數(shù): 215
門數(shù): 600000
電源電壓: 1.14 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 281-TFBGA,CSBGA
供應(yīng)商設(shè)備封裝: 281-CSP(10x10)
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IGLOO Device Family Overview
1-8
Revision 23
Each I/O module contains several input, output, and enable registers. These registers allow the
implementation of the following:
Single-Data-Rate applications
Double-Data-Rate applications—DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point
communications
IGLOO banks for the AGL250 device and above support LVPECL, LVDS, B-LVDS, and M-LVDS. B-LVDS
and M-LVDS can support up to 20 loads.
Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card
in a powered-up system.
Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed
when the system is powered up, while the component itself is powered down, or when power supplies
are floating.
Wide Range I/O Support
IGLOO devices support JEDEC-defined wide range I/O operation. IGLOO devices support both the
JESD8-B specification, covering 3 V and 3.3 V supplies, for an effective operating range of 2.7 V to
3.6 V, and JESD8-12 with its 1.2 V nominal, supporting an effective operating range of 1.14 V to 1.575 V.
Wider I/O range means designers can eliminate power supplies or power conditioning components from
the board or move to less costly components with greater tolerances. Wide range eases I/O bank
management and provides enhanced protection from system voltage spikes, while providing the flexibility
to easily run custom voltage applications.
Specifying I/O States During Programming
You can modify the I/O states during programming in FlashPro. In FlashPro, this feature is supported for
PDB files generated from Designer v8.5 or greater. See the FlashPro User’s Guide for more information.
Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have
limited display of Pin Numbers only.
1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during
programming.
2. From the FlashPro GUI, click PDB Configuration. A FlashPoint – Programming File Generator
window appears.
3. Click the Specify I/O States During Programming button to display the Specify I/O States During
Programming dialog box.
4. Sort the pins as desired by clicking any of the column headers to sort the entries by that header.
Select the I/Os you wish to modify (Figure 1-5 on page 1-9).
5. Set the I/O Output State. You can set Basic I/O settings if you want to use the default I/O settings
for your pins, or use Custom I/O settings to customize the settings for each pin. Basic I/O state
settings:
1 – I/O is set to drive out logic High
0 – I/O is set to drive out logic Low
Last Known State – I/O is set to the last value that was driven out prior to entering the
programming mode, and then held at that value during programming
Z -Tri-State: I/O is tristated
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M1AGL600V2-CSG281 功能描述:IC FPGA 1KB FLASH 600K 281-CSP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門陣列) 系列:IGLOO 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA(17x17)