
IGLOOe Low Power Flash FPGAs
Revision 13
2-21
HSTL (II)
15 mA5
High –0.3 VREF – 0.1
VREF + 0.1
3.6
0.4
VCCI – 0.4
15
SSTL2 (I)
15 mA
High –0.3 VREF – 0.2
VREF + 0.2
3.6
0.54
VCCI – 0.62 15
15
SSTL2 (II)
18 mA
High –0.3 VREF – 0.2
VREF + 0.2
3.6
0.35
VCCI – 0.43 18
18
SSTL3 (I)
14 mA
High –0.3 VREF – 0.2
VREF + 0.2
3.6
0.7
VCCI – 1.1 14
14
SSTL3 (II)
21 mA
High –0.3 VREF – 0.2
VREF + 0.2
3.6
0.5
VCCI – 0.9 21
21
Table 2-21 Summary of Maximum and Minimum DC Input and Output Levels (continued)
Applicable to Commercial and Industrial Conditions
I/O
Standard
Drive
Strength
Equivalent
Software
Default
Drive
Strength2
Slew
Rate
VIL
VIH
VOL
VOH
IOL1 IOH1
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
VmA mA
Notes:
1. Currents are measured at 85°C junction temperature.
2. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is
±100 A. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the
IBIS models.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-12 specification.
4. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.
5. Output drive strength is below JEDEC specification.
6. Output Slew Rates can be extracted from IBIS Models, http://www.microsemi.com/soc/download/ibis/default.aspx.