IGLOOe Low Power Flash FPGAs
Revision 13
2-99
Table 2-146 RAM512X18
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
Std.
Units
tAS
Address Setup Time
0.83
ns
tAH
Address Hold Time
0.16
ns
tENS
REN, WEN Setup Time
0.73
ns
tENH
REN, WEN Hold Time
0.08
ns
tDS
Input Data (WD) Setup Time
0.71
ns
tDH
Input Data (WD) Hold Time
0.36
ns
tCKQ1
Clock HIGH to New Data Valid on RD (output retained, WMODE = 0)
4.21
ns
tCKQ2
Clock HIGH to New Data Valid on RD (pipelined)
1.71
ns
tC2CRWH1
Address collision clk-to-clk delay for reliable read access after write on
same address; applicable to opening edge
0.35
ns
tC2CWRH1
Address collision clk-to-clk delay for reliable write access after read on
same address; applicable to opening edge
0.42
ns
tRSTBQ
RESET Low to Data Out Low on RD (flow-through)
2.06
ns
RESET Low to Data Out Low on RD (pipelined)
2.06
ns
tREMRSTB
RESET Removal
0.61
ns
tRECRSTB
RESET Recovery
3.21
ns
tMPWRSTB
RESET Minimum Pulse Width
0.68
ns
tCYC
Clock Cycle Time
6.24
ns
FMAX
Maximum Frequency
160
MHz
Notes:
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.