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參數(shù)資料
| 型號(hào)： | M24C16REA1T |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | DRAM |
| 英文描述： | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| 中文描述： | 該CAT24FC02是一個(gè)2 KB的EEPROM的國內(nèi)256個(gè)8位每字舉辦的串行CMOS |
| 文件頁數(shù)： | 10/25頁 |
| 文件大?。?/td> | 449K |
| 代理商： | M24C16REA1T |
M24C16, M24C08, M24C04, M24C02, M24C01
10/25
Figure 10. Read Mode Sequences
Note: The seven most significant bits of the Device Select Code of a Random Read (in the 1
st
and 3
rd
bytes) must be identical.
Read Operations
Read operations are performed independently of
the state of the Write Control (WC) signal.
The device has an internal address counter which
is incremented each time a byte is read.
Random Address Read
A dummy Write is first performed to load the ad-
dress into this address counter (as shown in
Fig-
ure 10.
) but
without
sending a Stop condition.
Then, the bus master sends another Start condi-
tion, and repeats the Device Select Code, with the
Read/Write bit (RW) set to 1. The device acknowl-
edges this, and outputs the contents of the ad-
dressed byte. The bus master must
not
acknowledge the byte, and terminates the transfer
with a Stop condition.
Current Address Read
For the Current Address Read operation, following
a Start condition, the bus master only sends a De-
vice Select Code with the Read/Write bit (RW) set
to 1. The device acknowledges this, and outputs
the byte addressed by the internal address
counter. The counter is then incremented. The bus
master terminates the transfer with a Stop condi-
tion, as shown in
Figure 10.
,
without
acknowledg-
ing the byte.
S
DEV SEL *
BYTE ADDR
S
DEV SEL
DATA OUT 1
AI01942
DATA OUT N
S
S
CURRENT
ADDRESS
READ
DEV SEL
DATA OUT
RANDOM
ADDRESS
READ
S
S
DEV SEL *
DATA OUT
SEQUENTIAL
CURRENT
READ
S
DATA OUT N
S
DEV SEL *
BYTE ADDR
SEQUENTIAL
RANDOM
READ
S
DEV SEL *
DATA OUT 1
S
ACK
R/W
NO ACK
ACK
R/W
ACK
ACK
R/W
ACK
ACK
ACK
NO ACK
R/W
NO ACK
ACK
ACK
R/W
ACK
ACK
R/W
ACK
NO ACK
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| M24C16REA3T | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
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| M24C16WDW3T | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| M24C16WDW6T | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
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