參數(shù)資料
型號: M24C32
廠商: 意法半導(dǎo)體
英文描述: 32K Serial IIC Bus EEPROM(32K串行IIC總線EEPROM)
中文描述: 32K的串行IIC總線的EEPROM(32K的串行總線EEPROM的國際進口許可證)
文件頁數(shù): 17/35頁
文件大?。?/td> 330K
代理商: M24C32
M24128, M24C64, M24C32
Device operation
17/35
Figure 9.
Write cycle polling flowchart using ACK
4.9
Minimizing system delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum Write time (t
w
) is
shown in
Table 17
and
Table 18
, but the typical time is shorter. To make use of this, a polling
sequence can be used by the bus master.
The sequence, as shown in
Figure 9
, is:
Initial condition: a Write cycle is in progress.
Step 1: the bus master issues a Start condition followed by a Device Select Code
(the first byte of the new instruction).
Step 2: if the device is busy with the internal Write cycle, no Ack will be returned
and the bus master goes back to Step 1. If the device has terminated the internal
Write cycle, it responds with an Ack, indicating that the device is ready to receive
the second part of the instruction (the first byte of this instruction having been sent
during Step 1).
WRITE Cycle
in Progress
AI01847C
Next
Operation is
Addressing the
Memory
START Condition
DEVICE SELECT
with RW = 0
ACK
Returned
YES
NO
YES
NO
ReSTART
STOP
DATA for the
WRITE Operation
DEVICE SELECT
with RW = 1
Send Address
and Receive ACK
First byte of instruction
with RW = 0 already
decoded by the device
YES
NO
START
Condition
Continue the
WRITE Operation
Continue the
Random READ Operation
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