- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄358972 > M24C64-DW6 (意法半導(dǎo)體) 1-Bit To 4-Bit Address Driver With 3-State Outputs 56-SSOP -40 to 85 PDF資料下載
參數(shù)資料
| 型號(hào)： | M24C64-DW6 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 1-Bit To 4-Bit Address Driver With 3-State Outputs 56-SSOP -40 to 85 |
| 中文描述： | 64Kbit和32Kbit串行IC總線的EEPROM |
| 文件頁(yè)數(shù)： | 8/26頁(yè) |
| 文件大?。?/td> | 394K |
| 代理商： | M24C64-DW6 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)當(dāng)前第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)
M24C64, M24C32
8/26
DEVICE OPERATION
The device supports the I
2
C protocol. This is sum-
marized in
Figure 5.
. Any device that sends data
on to the bus is defined to be a transmitter, and
any device that reads the data to be a receiver.
The device that controls the data transfer is known
as the bus master, and the other as the slave de-
vice. A data transfer can only be initiated by the
bus master, which will also provide the serial clock
for synchronization. The M24Cxx device is always
a slave in all communication.
Start Condition
Start is identified by a falling edge of Serial Data
(SDA) while Serial Clock (SCL) is stable in the
High state. A Start condition must precede any
data transfer command. The device continuously
monitors (except during a Write cycle) Serial Data
(SDA) and Serial Clock (SCL) for a Start condition,
and will not respond unless one is given.
Stop Condition
Stop is identified by a rising edge of Serial Data
(SDA) while Serial Clock (SCL) is stable and driv-
en High. A Stop condition terminates communica-
tion between the device and the bus master. A
Read command that is followed by NoAck can be
followed by a Stop condition to force the device
into the Stand-by mode. A Stop condition at the
end of a Write command triggers the internal Write
cycle.
Acknowledge Bit (ACK)
The acknowledge bit is used to indicate a success-
ful byte transfer. The bus transmitter, whether it be
bus master or slave device, releases Serial Data
(SDA) after sending eight bits of data. During the
9
th
clock pulse period, the receiver pulls Serial
Data (SDA) Low to acknowledge the receipt of the
eight data bits.
Data Input
During data input, the device samples Serial Data
(SDA) on the rising edge of Serial Clock (SCL).
For correct device operation, Serial Data (SDA)
must be stable during the rising edge of Serial
Clock (SCL), and the Serial Data (SDA) signal
must change onlywhen Serial Clock (SCL) is driv-
en Low.
Memory Addressing
To start communication between the bus master
and the slave device, the bus master must initiate
a Start condition. Following this, the bus master
sends the Device Select Code, shown in
Table 3.
(on Serial Data (SDA), most significant bit first).
The Device Select Code consists of a 4-bit Device
Type Identifier, and a 3-bit Chip Enable “Address”
(E2, E1, E0). To address the memory array, the 4-
bit Device Type Identifier is 1010b.
Up to eight memory devices can be connected on
a single I
2
C bus. Each one is given a unique 3-bit
code on the Chip Enable (E0, E1, E2) inputs.
When the Device Select Code is received, the de-
vice only responds if the Chip Enable Address is
the same as the value on the Chip Enable (E0, E1,
E2) inputs.
The 8
th
bit is the Read/Write bit (RW). This bit is
set to 1 for Read and 0 for Write operations.
If a match occurs on the Device Select code, the
corresponding device gives an acknowledgment
on Serial Data (SDA) during the 9
th
bit time. If the
device does not match the Device Select code, it
deselects itself from the bus, and goes into Stand-
by mode.
Table 6. Operating Modes
Note: 1. X =
V
IH
or V
IL
.
Mode
RW bit
WC
1
Bytes
Initial Sequence
Current Address Read
1
X
1
START, Device Select, RW = 1
Random Address Read
0
X
1
START, Device Select, RW = 0, Address
1
X
reSTART, Device Select, RW = 1
Sequential Read
1
X
≥
1
Similar to Current or Random Address Read
Byte Write
0
V
IL
1
START, Device Select, RW = 0
Page Write
0
V
IL
≤
32
START, Device Select, RW = 0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M24C64-DW6P | 1-Bit To 4-Bit Address Driver With 3-State Outputs 56-TSSOP -40 to 85 |
| M24C64-DW6T | 1-Bit To 4-Bit Address Driver With 3-State Outputs 56-SSOP -40 to 85 |
| M24C64-DW6TP | 1-Bit To 4-Bit Address Driver With 3-State Outputs 56-SSOP -40 to 85 |
| M24C64-MB3 | 16-Bit Transparent D-Type Latch With 3-State Outputs 48-TSSOP -40 to 85 |
| M24C64-MB3P | 16-Bit Transparent D-Type Latch With 3-State Outputs 48-SSOP -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M24C64-FCS6TP/K | 功能描述:電可擦除可編程只讀存儲(chǔ)器 64kB Serial I2C bus 1.7V 1MHz Fast Mode RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| M24C64-FCU6TP/TF | 功能描述:MEMORY 制造商:stmicroelectronics 系列:- 包裝:剪切帶（CT） 零件狀態(tài):停產(chǎn) 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:64K（8K x 8） 速度:1MHz 接口:I2C，2 線串口 電壓 - 電源:1.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C（TA） 封裝/外殼:4-XFBGA，WLCSP 供應(yīng)商器件封裝:4-WLCSP（0.80x0.67） 標(biāo)準(zhǔn)包裝:1 |
| M24C64-FDW5TP | 功能描述:電可擦除可編程只讀存儲(chǔ)器 電可擦除可編程只讀存儲(chǔ)器 S I2C 64k RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| M24C64-FDW6TP | 功能描述:電可擦除可編程只讀存儲(chǔ)器 64kB Serial I2C bus 1.7V 1MHz Fast Mode RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| M24C64-FMB6TG | 功能描述:電可擦除可編程只讀存儲(chǔ)器 128 Kbit 64 Kbit 1.7 V to 5.5 V RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。