參數(shù)資料
型號(hào): M24C64-DW6T
廠商: 意法半導(dǎo)體
英文描述: 1-Bit To 4-Bit Address Driver With 3-State Outputs 56-SSOP -40 to 85
中文描述: 64Kbit和32Kbit串行IC總線的EEPROM
文件頁數(shù): 25/26頁
文件大?。?/td> 394K
代理商: M24C64-DW6T
25/26
M24C64, M24C32
REVISION HISTORY
Table 23. Document Revision History
Date
Rev.
Description of Revision
22-Dec-1999
2.3
TSSOP8 package in place of TSSOP14 (pp 1, 2, OrderingInfo, PackageMechData).
28-Jun-2000
2.4
TSSOP8 package data corrected
31-Oct-2000
2.5
References to Temperature Range 3 removed from Ordering Information
Voltage range -S added, and range -R removed from text and tables throughout.
20-Apr-2001
2.6
Lead Soldering Temperature in the Absolute Maximum Ratings table amended
Write Cycle Polling Flow Chart using ACK illustration updated
References to PSDIP changed to PDIP and Package Mechanical data updated
16-Jan-2002
2.7
Test condition for I
LI
made more precise, and value of I
LI
for E2-E0 and WC added
-R voltage range added
02-Aug-2002
2.8
Document reformatted using new template.
TSSOP8 (3x3mm2 body size) package (MSOP8) added.
5ms write time offered for 5V and 2.5V devices
04-Feb-2003
2.9
SO8W package removed. -S voltage range removed
27-May-2003
2.10
TSSOP8 (3x3mm2 body size) package (MSOP8) removed
22-Oct-2003
3.0
Table of contents, and Pb-free options added. Minor wording changes in Summary
Description, Power-On Reset, Memory Addressing, Write Operations, Read Operations.
V
IL
(min) improved to -0.45V.
01-Jun-2004
4.0
Absolute Maximum Ratings for V
IO
(min) and V
CC
(min) improved. Soldering temperature
information clarified for RoHS compliant devices. Device Grade clarified
04-Nov-2004
5.0
Product List summary table added. Device Grade 3 added. 4.5-5.5V range is Not for New
Design. Some minor wording changes. AEC-Q100-002 compliance. t
NS
(max) changed.
V
IL
(min) is the same on all input pins of the device. Z
WCL
changed.
05-Jan-2005
6.0
UFDFPN8 package added. Small text changes.
相關(guān)PDF資料
PDF描述
M24C64-DW6TP 1-Bit To 4-Bit Address Driver With 3-State Outputs 56-SSOP -40 to 85
M24C64-MB3 16-Bit Transparent D-Type Latch With 3-State Outputs 48-TSSOP -40 to 85
M24C64-MB3P 16-Bit Transparent D-Type Latch With 3-State Outputs 48-SSOP -40 to 85
M24C64-MB3T 16-Bit Transparent D-Type Latch With 3-State Outputs 48-SSOP -40 to 85
M24C64-WMN3T The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
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