參數(shù)資料
型號: M24C64-MB6
廠商: 意法半導體
英文描述: 16-Bit Transparent D-Type Latch With 3-State Outputs 48-TSSOP -40 to 85
中文描述: 64Kbit和32Kbit串行IC總線的EEPROM
文件頁數(shù): 10/26頁
文件大?。?/td> 394K
代理商: M24C64-MB6
M24C64, M24C32
10/26
Page Write
The Page Write mode allows up to 32 bytes to be
written in a single Write cycle, provided that they
are all located in the same ’row’ in the memory:
that is, the most significant memory address bits
(b12-b5 for M24C64, and b11-b5 for M24C32) are
the same. If more bytes are sent than will fit up to
the end of the row, a condition known as ‘roll-over’
occurs. This should be avoided, as data starts to
become overwritten in an implementation depen-
dent way.
The bus master sends from 1 to 32 bytes of data,
each of which is acknowledged by the device if
Write Control (WC) is Low. If Write Control (WC) is
High, the contents of the addressed memory loca-
tion are not modified, and each data byte is fol-
lowed by a NoAck. After each byte is transferred,
the internal byte address counter (the 5 least sig-
nificant address bits only) is incremented. The
transfer is terminated by the bus master generat-
ing a Stop condition.
Figure 8. Write Mode Sequences with WC=0 (data write enabled)
S
S
BYTE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
DATA IN
WC
S
PAGE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
DATA IN 1
WC
DATA IN 2
AI01106C
PAGE WRITE
(cont'd)
WC (cont'd)
S
DATA IN N
ACK
R/W
ACK
ACK
ACK
ACK
ACK
ACK
ACK
R/W
ACK
ACK
相關(guān)PDF資料
PDF描述
M24C64-MB6P 16-Bit Transparent D-Type Latch With 3-State Outputs 56-BGA MICROSTAR JUNIOR -40 to 85
M24C64-MB6T 16-Bit Transparent D-Type Latch With 3-State Outputs 54-BGA MICROSTAR JUNIOR -40 to 85
M24C64-MB6TP 16-Bit Transparent D-Type Latch With 3-State Outputs 48-TSSOP -40 to 85
M24C64-MN3 16-Bit Transparent D-Type Latch With 3-State Outputs 48-SSOP -40 to 85
M24C64-MN3P 16-Bit Transparent D-Type Latch With 3-State Outputs 48-SSOP -40 to 85
相關(guān)代理商/技術(shù)參數(shù)
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