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參數(shù)資料
| 型號： | M24C64-WMN6TP |
| 廠商： | 意法半導體 |
| 元件分類： | DRAM |
| 英文描述： | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| 中文描述： | 該CAT24FC02是一個2 KB的EEPROM的國內(nèi)256個8位每字舉辦的串行CMOS |
| 文件頁數(shù)： | 11/26頁 |
| 文件大?。?/td> | 394K |
| 代理商： | M24C64-WMN6TP |
11/26
M24C64, M24C32
Figure 9. Write Cycle Polling Flowchart using ACK
Minimizing System Delays by Polling On ACK
During the internal Write cycle, the device discon-
nects itself from the bus, and writes a copy of the
data from its internal latches to the memory cells.
The maximum Write time (t
w
) is shown in
Table
16.
and
Table 17.
, but the typical time is shorter.
To make use of this, a polling sequence can be
used by the bus master.
The sequence, as shown in
Figure 9.
, is:
–
–
Initial condition: a Write cycle is in progress.
Step 1: the bus master issues a Start condition
followed by a Device Select Code (the first
byte of the new instruction).
Step 2: if the device is busy with the internal
Write cycle, no Ack will be returned and the
bus master goes back to Step 1. If the device
has terminated the internal Write cycle, it
responds with an Ack, indicating that the
device is ready to receive the second part of
the instruction (the first byte of this instruction
having been sent during Step 1).
–
WRITE Cycle
in Progress
AI01847C
Next
Operation is
Addressing the
Memory
START Condition
DEVICE SELECT
with RW = 0
ACK
Returned
YES
NO
YES
NO
ReSTART
STOP
DATA for the
WRITE Operation
DEVICE SELECT
with RW = 1
Send Address
and Receive ACK
First byte of instruction
with RW = 0 already
decoded by the device
YES
NO
START
Condition
Continue the
WRITE Operation
Continue the
Random READ Operation
相關PDF資料 |
PDF描述 |
|---|---|
| M24C64BN6T | 18-Bit Universal Bus Transceiver With 3-State Outputs 56-TSSOP -40 to 85 |
| M24C64DW3T | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| M24C64DW5T | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| M24C64DW6T | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| M24C64WBN3T | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M24C64-WMN6TP/P | 制造商:STMicroelectronics 功能描述:EEPROM SERL-I2C 64KBIT 8KX8 3.3V/5V 8PIN SO N - Tape and Reel |
| M24C64-WMN6TP-CUT TAPE | 制造商:ST 功能描述:M24C64 Series 64 Kb (8 K x 8) 2.5 V SMT Serial I? Bus EEPROM - SOIC-8 |
| M24D16161DA | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:16-Mbit (1M x 16) Pseudo Static RAM |
| M24D16161DA-70BIG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:16-Mbit (1M x 16) Pseudo Static RAM |
| M24D16161ZA | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:16-Mbit (1M x 16) Pseudo Static RAM |
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