參數(shù)資料
型號(hào): M25P16-VMW3TP
廠商: 意法半導(dǎo)體
元件分類: DRAM
英文描述: 4 Mbit Uniform Sector, Serial Flash Memory
中文描述: 4兆位統(tǒng)一部門,串行閃存
文件頁數(shù): 40/55頁
文件大小: 335K
代理商: M25P16-VMW3TP
DC and AC parameters
M25P16
40/55
AC characteristics (Grade 6)
Table 15.
Test conditions specified in
Table 10
and
Table 12
Symbol
Alt.
Parameter
Min.
Typ.
Max.
Unit
f
C
f
C
Clock Frequency
(1)
for the following instructions: FAST_READ,
PP, SE, BE, DP, RES, WREN, WRDI, RDID, RDSR, WRSR
Clock Frequency for READ instructions
Clock High Time
Clock Low Time
Clock Rise Time
(3)
(peak to peak)
Clock Fall Time
(3)
(peak to peak)
S Active Setup Time (relative to C)
S Not Active Hold Time (relative to C)
Data In Setup Time
Data In Hold Time
S Active Hold Time (relative to C)
S Not Active Setup Time (relative to C)
S Deselect Time
Output Disable Time
Clock Low to Output Valid
Output Hold Time
HOLD Setup Time (relative to C)
HOLD Hold Time (relative to C)
HOLD Setup Time (relative to C)
HOLD Hold Time (relative to C)
HOLD to Output Low-Z
HOLD to Output High-Z
Write Protect Setup Time
Write Protect Hold Time
S High to Deep Power-down Mode
S High to Standby Mode without Electronic Signature Read
S High to Standby Mode with Electronic Signature Read
Write Status Register Cycle Time
Page Program Cycle Time (256 Bytes)
D.C.
50
MHz
f
R
D.C.
9
9
0.1
0.1
5
5
2
5
5
5
100
20
MHz
ns
ns
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
μs
ms
t
CH(1)
t
CL(1)
t
CLCH(2)
t
CHCL(2)
t
SLCH
t
CHSL
t
DVCH
t
CHDX
t
CHSH
t
SHCH
t
SHSL
t
SHQZ(2)
t
CLQV
t
CLQX
t
HLCH
t
CHHH
t
HHCH
t
CHHL
t
HHQX(2)
t
HLQZ(2)
t
WHSL(4)
t
SHWL(4)
t
DP(2)
t
RES1(2)
t
RES2(2)
t
W
t
CLH
t
CLL
t
CSS
t
DSU
t
DH
t
CSH
t
DIS
t
V
t
HO
8
8
0
5
5
5
5
t
LZ
t
HZ
8
8
20
100
3
30
30
15
5
t
PP(5)
1.4
0.4+
n*1/256
1
17
5
ms
Page Program Cycle Time (n Bytes)
t
SE
t
BE
Sector Erase Cycle Time
Bulk Erase Cycle Time
3
s
s
40
1.
t
CH
+ t
CL
must be greater than or equal to 1/ f
C
Value guaranteed by characterization, not 100% tested in production.
2.
3.
Expressed as a slew-rate.
4.
Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
5.
When using the Page Program (PP) instruction to program consecutive Bytes, optimized timings are obtained with one
sequence including all the Bytes versus several sequences of only a few Bytes. (1
n
256)
相關(guān)PDF資料
PDF描述
M25P16-VMW6G 4 Mbit Uniform Sector, Serial Flash Memory
M25P16-VMW6P 4 Mbit Uniform Sector, Serial Flash Memory
M25P16-VMW6TG 4 Mbit Uniform Sector, Serial Flash Memory
M25P16-VMW6TP 4 Mbit Uniform Sector, Serial Flash Memory
M25P16-VME3G 4 Mbit Uniform Sector, Serial Flash Memory
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