參數(shù)資料
型號(hào): M27C800-120XM6TR
廠商: 意法半導(dǎo)體
英文描述: Octal Buffer/Driver With 3-State Outputs 20-TSSOP -40 to 85
中文描述: 8兆1兆x8或512KB的x16紫外線存儲(chǔ)器和OTP存儲(chǔ)器
文件頁數(shù): 10/18頁
文件大?。?/td> 171K
代理商: M27C800-120XM6TR
M27C800
10/18
Figure 8. Programming and Verify Modes AC Waveforms
tAVEL
VALID
AI01599
A0-A18
Q0-Q15
BYTEVPP
VCC
G
DATA IN
DATA OUT
E
tQVEL
tVPHAV
tVCHAV
tEHQX
tELEH
tGLQV
tQXGL
tGHQZ
tGHAX
PROGRAM
VERIFY
Figure 9. Programming Flowchart
AI01044B
n = 0
Last
Addr
VERIFY
E = 50
μ
s Pulse
++n
= 25
++ Addr
VCC = 6.25V, VPP = 12.5V
FAIL
CHECK ALL WORDS
BYTEVPP =VIH
1st: VCC = 6V
2nd: VCC = 4.2V
YES
NO
YES
NO
YES
NO
PRESTO III Programming Algorithm
The PRESTO III Programming Algorithm allows
the whole array to be programed with a guaran-
teed margin in a typical time of 26 seconds. Pro-
gramming with PRESTO III consists of applying a
sequence of 50μs program pulses to each word
until a correct verify occurs (see Figure 9). During
programing and verify operation a MARGIN
MODE circuit is automatically activated to guaran-
tee that each cell is programed with enough mar-
gin. No overprogram pulse is applied since the
verify in MARGIN MODE provides the necessary
margin to each programmed cell.
Program Inhibit
Programming of multiple M27C800s in parallel
with different data is also easily accomplished. Ex-
cept for E, all like inputs including G of the parallel
M27C800 may be common. A TTL low level pulse
applied to a M27C800's E input and V
PP
at 12.5V,
will program that M27C800. A high level E input in-
hibits the other M27C800s from being pro-
grammed.
Program Verify
A verify (read) should be performed on the pro-
grammed bits to determine that they were correct-
ly programmed. The verify is accomplished with E
at V
IH
and G at V
IL
, V
PP
at 12.5V and V
CC
at
6.25V.
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