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參數(shù)資料
| 型號(hào)： | M27V402-180N1TR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Quadruple 2-Input Positive-AND Gates 14-SOIC 0 to 70 |
| 中文描述： | 4兆位512KB的× 8 EPROM的低電壓檢察官辦公室 |
| 文件頁數(shù)： | 5/13頁 |
| 文件大?。?/td> | 120K |
| 代理商： | M27V402-180N1TR |
5/13
M27V405
Table 7. Read Mode DC Characteristics
(1)
(T
A
= 0 to 70°C, –20 to 70°C, –20 to 85°C or –40 to 85°C; V
CC
= 3.3V ± 10%; V
PP
= V
CC
)
Symbol
Parameter
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Maximum DC voltage on Output is V
CC
+0.5V.
Table 8A. Read Mode AC Characteristics
(1)
(T
A
= 0 to 70°C, –20 to 70°C, –20 to 85°C or –40 to 85°C; V
CC
= 3.3V ± 10%; V
PP
= V
CC
)
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Sampled only, not 100% tested.
Test Condition
Min
Max
Unit
I
LI
Input Leakage Current
0V
≤
V
IN
≤
V
CC
±10
μA
I
LO
Output Leakage Current
0V
≤
V
OUT
≤
V
CC
±10
μA
I
CC
Supply Current
E = V
IL
, G = V
IL
, I
OUT
= 0mA,
f = 5MHz, V
CC
≤
3.6V
15
mA
I
CC1
Supply Current (Standby) TTL
E = V
IH
1
mA
I
CC2
Supply Current (Standby) CMOS
E > V
CC
– 0.2V, V
CC
≤
3.6V
20
μA
I
PP
Program Current
V
PP
= V
CC
10
μA
V
IL
Input Low Voltage
–0.3
0.8
V
V
IH
(2)
Input High Voltage
2
V
CC
+ 1
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4
V
V
OH
Output High Voltage TTL
I
OH
= –400μA
2.4
V
Output High Voltage CMOS
I
OH
= –100μA
V
CC
– 0.7V
V
Symbol
Alt
Parameter
Test Condition
M27V405
Unit
-120
-150
Min
Max
Min
Max
t
AVQV
t
ACC
Address Valid to Output Valid
E = V
IL
, G = V
IL
120
150
ns
t
ELQV
t
CE
Chip Enable Low to Output Valid
G = V
IL
120
150
ns
t
GLQV
t
OE
Output Enable Low to Output Valid
E = V
IL
60
80
ns
t
EHQZ (2)
t
DF
Chip Enable High to Output Hi-Z
G = V
IL
0
50
0
50
ns
t
GHQZ (2)
t
DF
Output Enable High to Output Hi-Z
E = V
IL
0
50
0
50
ns
t
AXQX
t
OH
Address Transition to Output
Transition
E = V
IL
, G = V
IL
0
0
ns
by the falling and rising edges of E. The magnitude
of the transient current peaks is dependent on the
capacitive and inductive loading of the device at
the output.
The associated transient voltage peaks can be
suppressed by complying with the two line output
control and by properly selected decoupling ca-
pacitors. It is recommended that a 0.1μF ceramic
capacitor be used on every device between V
CC
and V
SS
. This should be a high frequency capaci-
tor of low inherent inductance and should be
placed as close to the device as possible. In addi-
tion, a 4.7μF bulk electrolytic capacitor should be
used between V
CC
and V
SS
for every eight devic-
es. The bulk capacitor should be located near the
power supply connection point.The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
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