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參數(shù)資料
| 型號(hào)： | M28F201-70XK3TR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 2 Mb 256K x 8, Chip Erase FLASH MEMORY |
| 中文描述： | 2 MB的256K × 8，芯片擦除閃存 |
| 文件頁(yè)數(shù)： | 7/21頁(yè) |
| 文件大?。?/td> | 179K |
| 代理商： | M28F201-70XK3TR |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)當(dāng)前第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)
Symbol
Alt
Parameter
Test Condition
M28F201
Unit
-70
-90
-120
-150
V
CC
=
5V
±
10%
V
CC
=
5V
±
10%
V
CC
=
5V
±
10%
V
CC
=
5V
±
10%
EPROM
Interface
EPROM
Interface
EPROM
Interface
EPROM
Interface
Min
Max
Min
Max
Min
Max
Min
Max
t
WHGL
Write Enable High to
Output Enable Low
6
6
6
6
μ
s
t
AVAV
t
RC
Read Cycle Time
E = V
IL
, G = V
IL
70
90
120
150
ns
t
AVQV
t
ACC
Address Valid to
Output Valid
E = V
IL
, G = V
IL
70
90
120
150
ns
t
ELQX
(1)
t
LZ
Chip Enable Low to
Output Transition
G = V
IL
0
0
0
0
ns
t
ELQV
t
CE
Chip Enable Low to
Output Valid
G = V
IL
70
90
120
150
ns
t
GLQX(1)
t
OLZ
Output Enable Low
to Output Transition
E = V
IL
0
0
0
0
ns
t
GLQV
t
OE
Output Enable Low
to Output Valid
E = V
IL
25
30
35
40
ns
t
EHQZ(1)
Chip Enable High to
Output Hi-Z
G = V
IL
0
25
0
30
0
30
0
35
ns
t
GHQZ(1)
t
DF
Output Enable High
to Output Hi-Z
E = V
IL
0
25
0
30
0
30
0
35
ns
t
AXQX
t
OH
Address Transition
to Output Transition
E = V
IL
, G = V
IL
0
0
0
0
ns
Note:
1. Sampled only,not 100% tested
Table 9. Read Only Mode ACCharacteristics
((T
A
= 0 to 70
°
C, –40 to 85
°
C or –40 to 125
°
C)
Erase and Erase Verify Modes.
The memory is
erased by first Programming all bytes to 00h, the
Erase command then erases them to FFh. The
Erase Verify command is then used to read the
memory byte-by-byte for a content of FFh. The
Erase Mode is set-up by writing 20h to the com-
mand register. The write cycle is then repeatedto
start the erase operation. Erasure starts on the
rising edge of W during this second cycle.Erase is
followed by an Erase Verify which reads an ad-
dressed byte.Erase Verify Mode is set-up bywrit-
ing A0h to the command register and at thesame
time supplying the address of the byte to be veri-
fied. The rising edge of W during the set-up of the
first Erase Verify Mode stops the Erase operation.
The following read cycle is madewith an internally
generated margin voltage applied; reading FFh
indicatesthatall bitsof theaddressedbyte arefully
erased. The whole contents of the memory are
verified by repeating the Erase Verify Operation,
first writing the set-up code A0h with the address
of thebyte to be verifiedand thenreading the byte
contentsin a secondread cycle.
As the Erasealgorithm flow chart shows,when the
data read during Erase Verify is not FFh, another
Erase operation is performed and verification con-
tinuesfromtheaddressofthelast verifiedbyte.The
command is terminated by writing another valid
command to the command register (for example
Programor Reset).
7/21
M28F201
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| M28F201-90XK3TR | 2 Mb 256K x 8, Chip Erase FLASH MEMORY |
| M28F201-120XK3TR | 2 Mb 256K x 8, Chip Erase FLASH MEMORY |
| M28F201-150XK3TR | 2 Mb 256K x 8, Chip Erase FLASH MEMORY |
| M28F201-70K3TR | 2 Mb 256K x 8, Chip Erase FLASH MEMORY |
| M28F201-90K3TR | 2 Mb 256K x 8, Chip Erase FLASH MEMORY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M28F201-70XK6R | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Mb 256K x 8, Chip Erase FLASH MEMORY |
| M28F201-70XK6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Mb 256K x 8, Chip Erase FLASH MEMORY |
| M28F201-70XN1R | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Mb 256K x 8, Chip Erase FLASH MEMORY |
| M28F201-70XN1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Mb 256K x 8, Chip Erase FLASH MEMORY |
| M28F201-70XN3R | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Mb 256K x 8, Chip Erase FLASH MEMORY |
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