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參數(shù)資料
| 型號(hào)： | M28LV64-200XP6 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | DRAM |
| 英文描述： | 64K 8K x 8 LOW VOLTAGE PARALLEL EEPROM with SOFTWARE DATA PROTECTION |
| 中文描述： | 64K的8K的× 8低電壓并聯(lián)EEPROM，帶有軟件數(shù)據(jù)保護(hù) |
| 文件頁(yè)數(shù)： | 4/18頁(yè) |
| 文件大小： | 127K |
| 代理商： | M28LV64-200XP6 |
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Mode
E
G
W
DQ0 - DQ7
Standby
1
X
X
Hi-Z
Output Disable
X
1
X
Hi-Z
Write Disable
X
X
1
Hi-Z
Read
0
0
1
Data Out
Write
0
1
0
Data In
Note:
1. 0 = V
IL
; 1 = V
IH
; X =V
IL
or V
IH
.
Table 3. OperatingModes
(1)
The M28LV64 outputs the Ready/Busy write
status,theM28LV64-aaaX(aaa=accesstime)has
no Ready/Busystatus and the relevant RB pin is
Not Connected (NC). The circuit has been de-
signed to offer a flexible microcontroller interface
featuring both hardware and software handshak-
ing with Ready/Busy,Data Polling and ToggleBit.
The M28LV64 supports 64 byte page write opera-
tion. A Software Data Protection (SDP) is also
possibleusing the standard JEDEC algorithm.
PINDESCRIPTION
Addresses (A0-A12).
The address inputs select
an 8-bit memory location during a read or write
operation.
Chip Enable (E).
The chip enable input must be
low to enableall read/writeoperations.WhenChip
Enableis high, power consumptionis reduced.
Output Enable (G).
TheOutput Enableinput con-
trols the data outputbuffersand is used to initiate
read operations.
DataIn/Out(DQ0- DQ7).
Datais written toorread
from the M28LV64 through the I/O pins.
Write Enable (W).
The Write Enableinputcontrols
the writing of data to the M28LV64.
Ready/Busy (RB).
Ready/Busy is an open drain
output that can be used to detect the end of the
internalwritecycle (thisfunctionappliesonlyto the
M28LV64).
OPERATION
In order to preventdata corruption andinadvertent
writeoperationsaninternalV
CC
comparatorinhibits
Write operation if V
CC
is below V
WI
(see Table 6).
Accesstothememory inwritemodeisallowedafter
a power-up as specifiedin Table6.
Read
TheM28LV64isaccessedlikea staticRAM. When
E and G are low with W high, the data addressed
is presented on the I/O pins. The I/O pinsare high
impedancewhen either G or E is high.
Write
Write operationsare initiated when both W and E
are low and G is high.TheM28LV64 supports both
E and W controlled write cycles. The Address is
latched by the falling edge of E or W which ever
occurslast and the Data on the rising edge of E or
W which ever occurs first. Once initiated the write
operationis internallytimed untilcompletion.
Page Write
Page write allows up to 64 bytes to be consecu-
tively latched into the memory prior to initiating a
programming cycle. All bytes must be located in a
single page address, that is A6-A12 must be the
samefor all bytes. The page writecan beinitiated
duringany byte write operation.
Following the first byte write instruction the host
may send another address and data with a mini-
mum data transfer rate of t
WHWH
(see Figure 13).
If atransitionof Eor Wisnotdetectedwithin t
WHWH
the internal programming cyclewill start.
DESCRIPTION
(cont’d)
4/18
M28LV64
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| M28LV64-250MS6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64K 8K x 8 LOW VOLTAGE PARALLEL EEPROM with SOFTWARE DATA PROTECTION |
| M28LV64-250N1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64K 8K x 8 LOW VOLTAGE PARALLEL EEPROM with SOFTWARE DATA PROTECTION |
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