參數(shù)資料
型號(hào): M29F040-120K5R
廠商: 意法半導(dǎo)體
英文描述: JFET-Input Low Power High Drive Quad Operational Amplifier 14-SOIC -55 to 125
中文描述: 4兆位512KB的× 8,統(tǒng)一座單電源閃存
文件頁(yè)數(shù): 10/31頁(yè)
文件大?。?/td> 232K
代理商: M29F040-120K5R
Symbol
Parameter
Test Condition
Min
Max
Unit
I
LI
Input Leakage Current
0V
V
IN
V
CC
±
1
μ
A
I
LO
Output Leakage Current
0V
V
OUT
V
CC
±
1
μ
A
I
CC1
Supply Current (Read)
E = V
IL
, G = V
IH
, f = 6MHz
15
mA
I
CC2
Supply Current (Standby) TTL
E = V
IH
1
mA
I
CC3
Supply Current (Standby) CMOS
E = V
CC
±
0.2V
50
μ
A
I
CC4
Supply Current (Program or Erase)
Byte Program,
Block Erase
20
mA
I
CC5
Supply Current
Chip Erase in progress
40
mA
V
IL
Input Low Voltage
–0.5
0.8
V
V
IH
Input High Voltage
2
V
CC
+ 0.5
V
V
OL
Output Low Voltage
I
OL
= 10mA
0.45
V
V
OH
Output High Voltage TTL
I
OH
= –2.5mA
2.4
V
Output High Voltage CMOS
I
OH
= –100
μ
A
V
CC
–0.4
V
I
OH
= –2.5mA
0.85 V
CC
V
V
ID
A9 Voltage (Electronic Signature)
11.5
12.5
V
I
ID
A9 Current (Electronic Signature)
A9 = V
ID
50
μ
A
V
LKO
Supply Voltage (Erase and
Program lock-out)
3.2
4.2
V
Table 11. DC Characteristics
(T
A
= 0 to 70
°
C, –20 to 85
°
C, –40 to 85
°
C or –40 to 125
°
C; V
CC
= 5V
±
10%)
Read Block Protection (RBP) instruction.
The
use of Read Electronic Signature (RSIG) command
also allows access to the Block Protection status
verify. After giving the RSIG command, A0 and A6
are set to V
IL
with A1 at V
IH
, while A16, A17 and
A18 define the block of the block to be verified. A
read in these conditions will output a 01h if block is
protected and a 00h if block is not protected.
This Read Block Protection is the only valid way to
check the protection status of a block. Neverthe-
less, it must not be used during the Block Protection
phase as a method to verify the block protection.
Please refer to Block Protection paragraph.
Chip Erase (CE) instruction.
This instruction uses
six write cycles. The Erase Set-up command 80h
is written to address 5555h on third cycle after the
two coded cycles. The Chip Erase Confirm com-
mand 10h is written at address 5555h on sixth cycle
after another two coded cycles. If the second com-
mand given is not an erase confirm or if the coded
cycles are wrong, the instruction aborts and the
device is reset to Read Array. It is not necessary to
program the array with 00h first as the P/E.C. will
automatically do this before erasing to FFh. Read
operations after the sixth rising edge of W or E
output the status register bits. During the execu-
tion of the erase by the P/E.C. the memory accepts
only the Reset (RST) command. Read of Data
Polling bit DQ7 returns ’0’, then ’1’ on completion.
The Toggle Bit DQ6 toggles during erase operation
and stops when erase is completed. After comple-
tion the Status Register bit DQ5 returns ’1’ if there
has been an Erase Failure because the erasure
has not been verified even after the maximum
number of erase cycles have been executed.
10/31
M29F040
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