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參數(shù)資料
| 型號： | M29F040-70XN1R |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 4 Mbit 512Kb x8, Uniform Block Single Supply Flash Memory |
| 中文描述： | 4兆位512KB的× 8，統(tǒng)一座單電源閃存 |
| 文件頁數(shù)： | 14/31頁 |
| 文件大小： | 232K |
| 代理商： | M29F040-70XN1R |
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Symbol
Alt
Parameter
M29F040
Unit
-70
-90
V
CC
= 5V
±
10%
V
CC
= 5V
±
10%
Standard
Interface
Standard
Interface
Min
Max
Min
Max
t
AVAV
t
WC
Address Valid to Next Address Valid
70
90
ns
t
ELWL
t
CS
Chip Enable Low to Write Enable Low
0
0
ns
t
WLWH
t
WP
Write Enable Low to Write Enable High
35
45
ns
t
DVWH
t
DS
Input Valid to Write Enable High
30
45
ns
t
WHDX
t
DH
Write Enable High to Input Transition
0
0
ns
t
WHEH
t
CH
Write Enable High to Chip Enable High
0
0
ns
t
WHWL
t
WPH
Write Enable High to Write Enable Low
20
20
ns
t
AVWL
t
AS
Address Valid to Write Enable Low
0
0
ns
t
WLAX
t
AH
Write Enable Low to Address Transition
45
45
ns
t
GHWL
Output Enable High to Write Enable Low
0
0
ns
t
VCHEL
t
VCS
V
CC
High to Chip Enable Low
50
50
μ
s
t
WHQV1
(1)
Write Enable High to Output Valid (Program)
10
10
μ
s
t
WHQV2
(1)
Write Enable High to Output Valid
(Block Erase)
1.0
30
1.0
30
sec
t
WHGL
t
OEH
Write Enable High to Output Enable Low
0
0
ns
Note:
1. Time is measured to Data Polling or Toggle Bit, t
= t
+ t
2. The temperature range –40 to 125
°
C is guaranteed at 70ns with High Speed Interface test condition and V
CC
= 5V
±
5%.
Table 13A. Write AC Characteristics, Write Enable Controlled
(T
A
= 0 to 70
°
C, –20 to 85
°
C, –40 to 85
°
C or –40 to 125
°
C)
(2)
Erase Resume (ER) instruction.
If an Erase Sus-
pend instruction was previously executed, the
erase operation may be resumed by giving the
command 30h, at any address, and without any
coded cycles.
Power Up
The memory Command Interface is reset on power
up to Read Array. Either E or W must be tied to V
IH
during Power-up to allow maximum security and
the possibility to write a command on the first rising
adge of E or W. Any write cycle initiation is blocked
when V
CC
is below V
LKO
.
Supply Rails
Normal precautions must be taken for supply volt-
age decoupling, each device in a system should
have the V
CC
rail decoupled with a 1.0
μ
F capacitor
close to the V
CC
and V
SS
pins. The PCB trace
widths should be sufficient to carry the V
CC
pro-
gram and erase currents required.
14/31
M29F040
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M29F040-70XN1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit 512Kb x8, Uniform Block Single Supply Flash Memory |
| M29F040-70XN3R | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit 512Kb x8, Uniform Block Single Supply Flash Memory |
| M29F040-70XN3TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit 512Kb x8, Uniform Block Single Supply Flash Memory |
| M29F040-70XN5R | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit 512Kb x8, Uniform Block Single Supply Flash Memory |
| M29F040-70XN5TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit 512Kb x8, Uniform Block Single Supply Flash Memory |
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