參數(shù)資料
型號(hào): M29F040-70XN3R
廠商: 意法半導(dǎo)體
英文描述: 4 Mbit 512Kb x8, Uniform Block Single Supply Flash Memory
中文描述: 4兆位512KB的× 8,統(tǒng)一座單電源閃存
文件頁數(shù): 12/31頁
文件大?。?/td> 232K
代理商: M29F040-70XN3R
Symbol
Alt
Parameter
Test Condition
M29F040
Unit
-120
-150
V
CC
= 5V
±
10% V
CC
= 5V
±
10%
Standard
Interface
Standard
Interface
Min
Max
Min
Max
t
AVAV
t
RC
Address Valid to Next Address Valid
E = V
IL
, G = V
IL
120
150
ns
t
AVQV
t
ACC
Address Valid to Output Valid
E = V
IL
, G = V
IL
120
150
ns
t
ELQX
(1)
t
LZ
Chip Enable Low to Output Transition
G = V
IL
0
0
ns
t
ELQV
(2)
t
CE
Chip Enable Low to Output Valid
G = V
IL
120
150
ns
t
GLQX
(1)
t
OLZ
Output Enable Low to Output
Transition
E = V
IL
0
0
ns
t
GLQV
(2)
t
OE
Output Enable Low to Output Valid
E = V
IL
50
55
ns
t
EHQX
t
OH
Chip Enable High to Output
Transition
G = V
IL
0
0
ns
t
EHQZ
(1)
t
HZ
Chip Enable High to Output Hi-Z
G = V
IL
30
35
ns
t
GHQX
t
OH
Output Enable High to Output
Transition
E = V
IL
0
0
ns
t
GHQZ
(1)
t
DF
Output Enable High to Output Hi-Z
E = V
IL
30
35
ns
t
AXQX
t
OH
Address Transition to Output
Transition
E = V
IL
, G = V
IL
20
20
ns
Notes:
1. Sampled only, not 100% tested.
2. G may be delayed by up to t
ELQV
- t
GLQV
after the falling edge of E without increasing t
ELQV
.
Table 12B. Read AC Characteristics
(T
A
= 0 to 70
°
C, –20 to 85
°
C, –40 to 85
°
C or –40 to 125
°
C)
Program (PG) instruction.
The memory can be
programmed Byte-by-Byte. This instruction uses
four write cycles. The Program command A0h is
written on the third cycle after two coded cycles. A
fourth write operation latches the Address on the
falling edge of W or E and the Data to be written
on its rising edge and starts the P/E.C. During the
execution of the program by the P/E.C., the mem-
ory will not accept any instruction. Read operations
output the status bits after the programming has
started. The status bits DQ5, DQ6 and DQ7 allow
a check of the status of the programming operation.
Memory programming is made only by writing ’0’ in
place of ’1’ in a Byte.
Erase Suspend (ES) instruction.
The Block
Erase operation may be suspended by this instruc-
tion which consists of writing the command 0B0h
without any specific address code. No coded cycles
are required. It allows reading of data from another
block while erase is in progress. Erase suspend is
accepted only during the Block Erase instruction
execution and defaults to read array mode. Writing
this command during Erase timeout will, in addition
to suspending the erase, terminate the timeout.
The Toggle Bit DQ6 stops toggling when the P/E.C.
is suspended. Toggle Bit status must be monitored
at an address out of the block being erased. Toggle
Bit will stop toggling between 0.1
μ
s and 15
μ
s after
the Erase Suspend (ES) command has been writ-
ten.
The M29F040 will then automatically set to Read
Memory Array mode. When erase is suspended,
Read from blocks being erased will output invalid
data, Read from block not being erased is valid.
During the suspension the memory will respond
only to Erase Resume (ER) and Reset (RST) in-
structions. RST command will definitively abort
erasure and result in the invalid data in the blocks
being erased.
12/31
M29F040
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