參數(shù)資料
型號(hào)： M29F080A-70M3T
廠商： 意法半導(dǎo)體
英文描述： Digital General Purpose Timer; RoHS Compliant: Yes
中文描述： 8兆1兆× 8，統(tǒng)一座單電源閃存
文件頁(yè)數(shù)： 4/21頁(yè)
文件大小： 131K
代理商： M29F080A-70M3T
M29F080A
4/21
A 0.1
μ
F capacitor should be connected between
the V
CC
Supply Voltage pin and the V
SS
Ground
pin to decouple the current surges from the power
supply. The PCB track widthsmust be sufficient to
carry the currents required during program and
erase operations, I
CC4
.
V
SS
Ground.
The V
SS
Ground is the reference for
all voltage measurements.
BUS OPERATIONS
There arefive standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby and Automatic Standby. See
Table 4, Bus Operations, for a summary. Typically
glitches of less than 5ns on Chip Enable or Write
Enable are ignored by the memory and do not af-
fect bus operations.
Bus Read.
Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs, applying a Low signal, V
IL
, to Chip Enable
and Output Enable and keeping Write Enable
High, V
IH
. The Data Inputs/Outputs will output the
value, see Figure 8, Read Mode AC Waveforms,
and Table 11, Read ACCharacteristics, for details
of when the output becomes valid.
Bus Write.
Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or WriteEnable, whichever occurs first.OutputEn-
able must remain High, V
IH
, during the whole Bus
Write operation. See Figures 9 and 10, Write AC
Waveforms, and Tables 12 and 13, Write AC
Characteristics, for details of the timing require-
ments.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V
IL
, for at least
t
PLPX
. After Reset/Block Temporary Unprotect
goes High, V
IH
, the memory will be ready for Bus
Read and Bus Write operations after t
PHEL
or
t
RHEL
, whichever occurs last. See theReady/Busy
Output section, Table 14 and Figure 11, Reset/
Temporary Unprotect AC Characteristics for more
details.
Holding RP at V
ID
will temporarily unprotect the
protected blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from V
IH
to V
ID
must be slower than
t
PHPHH
.
Ready/Busy Output (RB).
The Ready/Busy pin
is anopen-drain output that can beused to identify
when the memory array can be read. Ready/Busy
is high-impedanceduring Read mode, Auto Select
mode and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes high-impedance. See Table 14 and Figure
11, Reset/Temporary Unprotect AC Characteris-
tics.
During Program or Erase operations Ready/Busy
is Low, V
OL
. Ready/Busy will remain Low during
Read/Reset commands or Hardware Resets until
the memory is ready to enter Read mode.
The use of an open-drain output allows the Ready/
Busy pins from severalmemories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
V
CC
Supply Voltage.
The V
CC
Supply Voltage
supplies the power for all operations (Read, Pro-
gram, Erase etc.).
The Command Interface is disabled when the V
CC
Supply Voltage is less than the Lockout Voltage,
V
LKO
. Thisprevents Bus Write operations from ac-
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
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