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參數(shù)資料
| 型號： | M29F102BB55N1T |
| 廠商： | 意法半導體 |
| 英文描述： | 1 Mbit 64Kb x16, Boot Block Single Supply Flash Memory |
| 中文描述： | 1兆位64Kb的x16插槽，啟動座單電源閃存 |
| 文件頁數(shù)： | 6/24頁 |
| 文件大?。?/td> | 432K |
| 代理商： | M29F102BB55N1T |
M29F102BB
6/24
SIGNAL DESCRIPTIONS
See
Figure 2., Logic Diagram
, and
Table
1., Signal Names
, for a brief overview of the sig-
nals connected to this device.
Address Inputs (A0-A15).
The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ15).
The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations DQ0-DQ7 represent the com-
mands sent to the Command Interface of the inter-
nal state machine; the Command Interface does
not use DQ8-DQ15 to decode the commands.
Chip Enable (E).
The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
High, V
IH
, all other pins are ignored.
Output Enable (G).
The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W).
The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
Reset/Block Temporary Unprotect (RP).
The Re-
set/Block Temporary Unprotect pin can be used to
apply a Hardware Reset to the memory or to tem-
porarily unprotect all blocks that have been pro-
tected.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V
IL
, for at least
t
PLPX
. After Reset/Block Temporary Unprotect
goes High, V
IH
, the memory will be ready for Bus
Read and Bus Write operations after t
PHEL
or t
PLYH
, whichever occurs last. See
Table
13., Write AC Characteristics, Chip Enable Con-
trolled (TA = 0 to 70 °C)
and
Figure 12., Reset/
Block Temporary Unprotect AC Waveforms
.
Holding RP at V
ID
will temporarily unprotect the
protected blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from V
IH
to V
ID
must be slower than
t
PHPHH
.
Reset/Block Temporary Unprotect can be left un-
connected. A weak internal pull-up resistor en-
sures that the memory always operates correctly.
V
CC
Supply Voltage.
The V
CC
Supply Voltage
supplies the power for all operations (Read, Pro-
gram, Erase etc.).
The Command Interface is disabled when the V
CC
Supply Voltage is less than the Lockout Voltage,
V
LKO
. This prevents Bus Write operations from ac-
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
A 0.1μF capacitor should be connected between
the V
CC
Supply Voltage pin and the V
SS
Ground
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program and
erase operations, I
CC3
.
Vss Ground.
The V
SS
Ground is the reference
for all voltage measurements.
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