參數(shù)資料
型號： M29W004B-90N5TR
廠商： 意法半導(dǎo)體
英文描述： 4 Mbit 512Kb x8, Boot Block Low Voltage Single Supply Flash Memory
中文描述： 4兆位512KB的× 8，啟動塊低壓單電源閃存
文件頁數(shù)： 9/30頁
文件大?。?/td> 222K
代理商： M29W004B-90N5TR
Mne.
Instr.
Cyc.
1st Cyc.
2nd Cyc. 3rd Cyc.
4th Cyc.
5th Cyc.
6th Cyc.
7th Cyc.
RD
(2,4)
Read/Reset
Memory
Array
1+
Addr.
(3,7)
X
Read Memory Array until a new write cycle is initiated.
Data
F0h
3+
Addr.
(3,7)
5555h
2AAAh
5555h
Read Memory Array until a new write cycle
is initiated.
Data
AAh
55h
F0h
AS
(4)
Auto Select
3+
Addr.
(3,7)
5555h
2AAAh
5555h
Read Electronic Signature or Block
Protection Status until a new write cycle is
initiated. See Note 5 and 6.
Data
AAh
55h
90h
PG
Program
4
Addr.
(3,7)
5555h
2AAAh
5555h
Program
Address
Read Data Polling or Toggle Bit
until Program completes.
Data
AAh
55h
A0h
Program
Data
BE
Block Erase
6
Addr.
(3,7)
5555h
2AAAh
5555h
5555h
2AAAh
Block
Address
Additional
Block
(8)
Data
AAh
55h
80h
AAh
55h
30h
30h
CE
Chip Erase
6
Addr.
(3,7)
5555h
2AAAh
5555h
5555h
2AAAh
5555h
Note 9
Data
AAh
55h
80h
AAh
55h
10h
ES
(10)
Erase
Suspend
1
Addr.
(3,7)
X
Read until Toggle stops, then read all the data needed from any
Block(s) not being erased then Resume Erase.
Data
B0h
ER
Erase
Resume
1
Addr.
(3,7)
X
Read Data Polling or Toggle Bits until Erase completes or Erase
is suspended another time
Data
30h
Notes:
1. Commands not interpreted in this table will default to read array mode.
2. A wait of t
is necessary after a Read/Reset command if the memory was in an Erase or Program mode
before starting any new operation (See Table 14 and Figure 9).
3. X = Don’t Care.
4. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after
the command cycles.
5. Signature Address bits A0, A1 at V
IL
will output Manufacturer code (20h). Address bits A0 at V
IH
and A1 at V
IL
will output
Device code.
6. Block Protection Address: A0 at V
, A1 at V
and A13-A18 within the Block will output the Block Protection status.
7. For Coded cycles address inputs A15-A18 are don’t care.
8. Optional, additional Blocks addresses must be entered within the erase timeout delay after last write entry, timeout status
can be verified through DQ3 value (see Erase Timer Bit DQ3 description). When full command is entered, read Data Polling
or Toggle bit until Erase is completed or suspended.
9. Read Data Polling, Toggle bits or RB until Erase completes.
10.During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased.
Table 8. Instructions
(1)
9/30
M29W004T, M29W004B
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