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參數(shù)資料
| 型號： | M29W008ET70N1F |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Low Noise High-Speed Precision Single Supply Operational Amplifier 8-SOIC |
| 中文描述： | 8兆（1兆× 8，引導(dǎo)塊）3V電源快閃記憶體 |
| 文件頁數(shù)： | 10/43頁 |
| 文件大?。?/td> | 282K |
| 代理商： | M29W008ET70N1F |
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2 Signal descriptions
M29W008ET, M29W008EB
10/43
2
Signal descriptions
See
Figure 2: Logic diagram
and
Table 1: Signal Names
, for a brief overview of the signals
connected to this device.
2.1
Address Inputs (A0-A19)
The address inputs for the memory array are latched during a Bus Write operation on the falling
edge of Chip Enable, E or Write Enable, W. When A9 is raised to V
ID
, either a Read Electronic
Signature Manufacturer or Device Code, Block Protection Status or a Write Block Protection or
Block Unprotection is enabled depending on the combination of levels on A0, A1 A6, A12 and
A15.
2.2
Data Input/Outputs (DQ0-DQ7)
During Bus Write operations, the Data Inputs/Outputs input the data to be programmed in the
memory array or a command to be written to the Command Interface. Both are latched on the
rising edge of Chip Enable, E or Write Enable, W. The Data Inputs/Outputs output the data
stored at the selected address during a Bus Read operation, the Electronic Signature
(Manufacturer or Device codes), the Block Protection Status or the Data Polling bit (DQ7),
Toggle Bits (DQ6) and DQ2), Error bit (DQ5) or Erase Timer bit (DQ3) of the Status Register.
Outputs are valid when Chip Enable, E and Output Enable, G are active. The output is high
impedance when the chip is deselected or the outputs are disabled and when RP is Low.
2.3
Chip Enable (E)
The Chip Enable, E, activates the memory control logic, input buffers, decoders and sense
amplifiers. When Chip Enable is High, V
IH
, the memory is deselected and the power
consumption is reduced to the Standby level. The Chip Enable, E, can also be used to control
Write operations to the command register and to the memory array, while W remains Low. The
Chip Enable must be forced to V
ID
during Block Unprotection operations.
2.4
Output Enable (G)
The Output Enable, G, gates the outputs through the data buffers during a Bus Read operation.
When G is High, V
IH
, the outputs are high impedance. G must be forced to V
ID
during Block
Protection and Unprotection operations.
2.5
Write Enable (W)
This Write Enable, W, controls write operations of the memory’s Command Interface.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M29W008ET70N6E | Low Noise High-Speed Precision Single Supply Operational Amplifier 8-SOIC |
| M29W008ET70N6F | Low Noise High-Speed Precision Single Supply Operational Amplifier 8-SOIC |
| M29W008EB90N1E | 8 Mbit (1Mb x 8, Boot Block) 3V Supply Flash Memory |
| M29W008EB90N1F | 8 Mbit (1Mb x 8, Boot Block) 3V Supply Flash Memory |
| M29W008EB90N6E | 8 Mbit (1Mb x 8, Boot Block) 3V Supply Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M29W008ET70N6E | 制造商:Micron Technology Inc 功能描述:FLASH TOP BLOCK 8MB SMD 29W008 |
| M29W008ET70N6F | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit (1Mb x 8, Boot Block) 3V Supply Flash Memory |
| M29W008ET90N1E | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit (1Mb x 8, Boot Block) 3V Supply Flash Memory |
| M29W008ET90N1F | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit (1Mb x 8, Boot Block) 3V Supply Flash Memory |
| M29W008ET90N6E | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit (1Mb x 8, Boot Block) 3V Supply Flash Memory |
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