參數(shù)資料
型號(hào)： M29W008ET90N1F
廠商： 意法半導(dǎo)體
英文描述： 8 Mbit (1Mb x 8, Boot Block) 3V Supply Flash Memory
中文描述： 8兆（1兆× 8，引導(dǎo)塊）3V電源快閃記憶體
文件頁(yè)數(shù)： 12/43頁(yè)
文件大?。?/td> 282K
代理商： M29W008ET90N1F
3 Bus Operations
M29W008ET, M29W008EB
12/43
3
Bus Operations
There are 5 standard bus operations that control the device. These are Bus Read, us Write,
Output Disable, Standby and Automatic Standby. See
Table 2: Bus Operations
, for a summary.
Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory
and do not affect the bus operations.
3.1
Standard bus operations
3.1.1
Bus Read
Bus Read operations are used to output the contents of the Memory Array, the Electronic
Signature, the Status Register or the Block Protection Status. Both Chip Enable E and Output
Enable G must be Low in order to read the output of the memory. A new Bus Read operation is
initiated either on the falling edge of Chip Enable, E, or on any address transition with E at V
IL
.
See
Figure 10: Read Mode AC Waveforms
, and
Table 10: Read AC Characteristics
for details
of the timing requirements.
3.1.2
Bus Write
Bus Write operations are used to write to the Command Interface or to latch input data to be
programmed. A valid Bus Write operation begins by setting the desired address on the Address
Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the
Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first.
Output Enable must remain High, V
IH
, during the whole Bus Write operation.
See Figures
11
and
12
, Write AC Waveforms and Tables
11
and
12
, Write AC Characteristics,
for details of the timing requirements.
3.1.3
Output Disable
The data outputs are high impedance when the Output Enable G is High with Write Enable W
High.
3.1.4
Standby
The memory is in Standby mode when Chip Enable, E, is High and the Program/Erase
Controller is idle. The Supply Current is reduced to the Standby Supply Current, I
CC2
, and the
outputs are high impedance, independent of the Output Enable G or Write Enable W inputs.
3.1.5
Automatic Standby
If CMOS levels (V
CC
± 0.2V) are used to drive the bus and if the bus is inactive (no address
transition, E = V
IL
) during 150ns or more, the memory automatically enters a Automatic
Standby mode where the Supply Current is reduced to the Standby Supply Current, I
CC2
. The
Inputs/Outputs will still output data if a Bus Read operation is in progress.
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