參數(shù)資料
型號: M29W008T-100N6TR
廠商: 意法半導(dǎo)體
英文描述: TV 22C 22#22D PIN RECP
中文描述: 8兆1兆× 8,啟動塊低壓單電源閃存
文件頁數(shù): 18/30頁
文件大?。?/td> 219K
代理商: M29W008T-100N6TR
Symbol
Alt
Parameter
M29W008T / M29W008B
Unit
-90
-100
V
CC
= 3.0V to 3.6V
C
L
= 30pF
V
CC
= 2.7V to 3.6V
C
L
= 30pF
Min
Max
Min
Max
t
AVAV
t
WC
Address Valid to Next Address Valid
90
100
ns
t
ELWL
t
CS
Chip Enable Low to Write Enable Low
0
0
ns
t
WLWH
t
WP
Write Enable Low to Write Enable High
45
50
ns
t
DVWH
t
DS
Input Valid to Write Enable High
45
50
ns
t
WHDX
t
DH
Write Enable High to Input Transition
0
0
ns
t
WHEH
t
CH
Write Enable High to Chip Enable High
0
0
ns
t
WHWL
t
WPH
Write Enable High to Write Enable Low
30
30
ns
t
AVWL
t
AS
Address Valid to Write Enable Low
0
0
ns
t
WLAX
t
AH
Write Enable Low to Address Transition
45
50
ns
t
GHWL
Output Enable High to Write Enable Low
0
0
ns
t
VCHEL
t
VCS
V
CC
High to Chip Enable Low
50
50
μ
s
t
WHGL
t
OEH
Write Enable High to Output Enable Low
0
0
ns
t
PHPHH
(1,2)
t
VIDR
RP Rise Time to V
ID
500
500
ns
t
PLPX
t
RP
RP Pulse Width
500
500
ns
t
WHRL
(1)
t
BUSY
Program Erase Valid to RB Delay
90
90
ns
t
PHWL (1)
t
RSP
RP High to Write Enable Low
4
4
μ
s
Notes:
1. Sample only, not 100% tested.
2. This timing is for Temporary Block Unprotection operation.
Table 15A. Write AC Characteristics, Write Enable Controlled
(T
A
= 0 to 70
°
C, –20 to 85
°
C or –40 to 85
°
C)
Block Erase (BE) Instruction
. This instruction
uses a minimum of six write cycles. The Erase
Set-up command 80h is written to address 5555h
on third cycle after the two Coded cycles. The Block
Erase Confirm command 30h is similarly written on
the sixth cycle after another two Coded cycles.
During the input of the second command an ad-
dress within the block to be erased is given and
latched into the memory. Additional block Erase
Confirm commands and block addresses can be
written subsequently to erase other blocks in par-
allel, without further Coded cycles. The erase will
start after the erase timeout period (see Erase
Timer Bit DQ3 description). Thus, additional Erase
Confirm commands for other blocks must be given
within this delay. The input of a new Erase Confirm
command will restart the timeout period. The status
of the internal timer can be monitored through the
level of DQ3, if DQ3 is ’0’ the Block Erase Com-
mand has been given and the timeout is running, if
DQ3 is ’1’, the timeout has expired and the P/E.C.
is erasing the Block(s). If the second command
given is not an erase confirm or if the Coded cycles
are wrong, the instruction aborts, and the device is
reset to Read Array. It is not necessary to program
the block with 00h as the P/E.C. will do this auto-
matically before to erasing to FFh. Read operations
after the sixth rising edge of W or E output the
status register status bits.
18/30
M29W008T, M29W008B
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