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參數(shù)資料
| 型號： | M29W200BT120M1T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 2 Mbit 256Kb x8 or 128Kb x16, Boot Block Low Voltage Single Supply Flash Memory |
| 中文描述： | 2兆位的256Kb x8或128KB的x16插槽，引導(dǎo)塊低壓單電源閃存 |
| 文件頁數(shù)： | 5/22頁 |
| 文件大?。?/td> | 144K |
| 代理商： | M29W200BT120M1T |
5/22
M29W200BT, M29W200BB
Table 5. Bus Operations, BYTE = V
IL
Note: X = V
IL
or V
IH
.
Table 6. Bus Operations, BYTE = V
IH
Note: X = V
IL
or V
IH
.
Operation
E
G
W
Address Inputs
DQ15A–1, A0-A16
Data Inputs/Outputs
DQ14-DQ8
DQ7-DQ0
Bus Read
V
IL
V
IL
V
IH
Cell Address
Hi-Z
Data Output
Bus Write
V
IL
V
IH
V
IL
Command Address
Hi-Z
Data Input
Output Disable
X
V
IH
V
IH
X
Hi-Z
Hi-Z
Standby
V
IH
X
X
X
Hi-Z
Hi-Z
Read Manufacturer
Code
V
IL
V
IL
V
IH
A0 = V
IL
, A1 = V
IL
, A9 = V
ID
,
Others V
IL
or V
IH
Hi-Z
20h
Read Device Code
V
IL
V
IL
V
IH
A0 = V
IH
, A1 = V
IL
, A9 = V
ID
,
Others V
IL
or V
IH
Hi-Z
51h (M29W200BT)
57h (M29W200BB)
Operation
E
G
W
Address Inputs
A0-A16
Data Inputs/Outputs
DQ15A–1, DQ14-DQ0
Bus Read
V
IL
V
IL
V
IH
Cell Address
Data Output
Bus Write
V
IL
V
IH
V
IL
Command Address
Data Input
Output Disable
X
V
IH
V
IH
X
Hi-Z
Standby
V
IH
X
X
X
Hi-Z
Read Manufacturer
Code
V
IL
V
IL
V
IH
A0 = V
IL
, A1 = V
IL
, A9 = V
ID
,
Others V
IL
or V
IH
0020h
Read Device Code
V
IL
V
IL
V
IH
A0 = V
IH
, A1 = V
IL
, A9 = V
ID
,
Others V
IL
or V
IH
0051h (M29W200BT)
0057h (M29W200BB)
BUS OPERATIONS
There are five standard busoperations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby and Automatic Standby. See
Tables 5 and 6, Bus Operations, for a summary.
Typically glitches of less than 5ns on Chip Enable
or Write Enableare ignoredby the memory and do
not affect bus operations.
Bus Read.
Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs, applying a Low signal, V
IL
, to Chip Enable
and Output Enable and keeping Write Enable
High, V
IH
. The Data Inputs/Outputs will output the
value, see Figure 8, Read Mode AC Waveforms,
and Table 14, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write.
Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the CommandInterface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or WriteEnable, whichever occurs first.OutputEn-
able must remain High, V
IH
, during the whole Bus
Write operation. See Figures 9 and 10, Write AC
Waveforms, and Tables 15 and 16, Write AC
Characteristics, for details of the timing require-
ments.
Output Disable.
The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, V
IH
.
Standby.
When Chip Enable is High, V
IH
, the
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high-imped-
ance state. To reduce the Supply Current to the
Standby Supply Current, I
CC2
, Chip Enableshould
be held within V
CC
±
0.2V.For the Standby current
level see Table 13, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, I
CC3
, for Programor Erase operations un-
til the operation completes.
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