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參數(shù)資料
| 型號(hào)： | M29W400DB45N6E |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 4 Mbit (512Kb x8 or 256Kb x16, Boot Block) 3V Supply Flash Memory |
| 中文描述： | 4兆位（512KB的x8或256Kb的x16插槽，引導(dǎo)塊）3V電源快閃記憶體 |
| 文件頁數(shù)： | 8/22頁 |
| 文件大?。?/td> | 146K |
| 代理商： | M29W400DB45N6E |
M29W400BT, M29W400BB
8/22
Unlock Bypass Command.
The Unlock Bypass
command is used in conjunction with the Unlock
Bypass Program command to program the memo-
ry. When the access time to the device is long (as
with some EPROM programmers) considerable
time saving can be made by using these com-
mands. Three Bus Write operations are required
to issue the Unlock Bypass command.
Once the Unlock Bypass command has been is-
sued the memory will only accept the Unlock By-
pass Program command and the Unlock Bypass
Reset command. The memory can be readas if in
Read mode.
Unlock Bypass Program Command.
The
lock Bypass Program command can be used to
program one address in memory at a time. The
command requires two Bus Write operations, the
final write operation latches the address and data
in the internal state machine and starts the Pro-
gram/Erase Controller.
The Program operation using the Unlock Bypass
Program command behaves identically to the Pro-
gram operation using the Program command. A
protected block cannot be programmed; the oper-
ation cannot be aborted and theStatus Register is
read. Errors must be reset using the Read/Reset
command, which leaves the device in Unlock By-
pass Mode.See the Program command for details
on the behavior.
Unlock Bypass Reset Command.
The
Bypass Reset command can be used to return to
Read/Reset mode from Unlock Bypass Mode.
Two BusWrite operationsare required to issuethe
Unlock Bypass Reset command.
Chip Erase Command.
The Chip Erase com-
mand canbeused to erasethe entirechip. Six Bus
Write operations are required to issue the Chip
Erase Command and start the Program/Erase
Controller.
If any blocks are protected then these are ignored
and all the other blocks are erased. If all of the
blocks are protected the Chip Erase operation ap-
pears tostart but will terminate withinabout100
μ
s,
leaving the data unchanged. No error condition is
given when protected blocks are ignored.
During the erase operation the memory will ignore
all commands. It is not possible to issue any com-
mand to abort the operation. Typical chip erase
times are given in Table 9. All Bus Read opera-
tions during the Chip Erase operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
Un-
Unlock
After the Chip Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read Mode.
TheChip Erase Command sets allof the bits inun-
protected blocks of the memory to ’1’. All previous
data is lost.
Block Erase Command.
The Block Erase com-
mand can be used to erase a list of one or more
blocks. Six Bus Write operations are required to
select the first block in the list. Each additional
block in the list can be selected by repeating the
sixth Bus Write operation using the address of the
additional block. The Block Erase operation starts
the Program/Erase Controller about 50
μ
s after the
last Bus Write operation. Once the Program/Erase
Controller starts it is not possible to select any
more blocks. Each additional block must therefore
be selected within 50
μ
s of the last block. The 50
μ
s
timer restartswhen an additionalblock is selected.
The Status Register can be read after the sixth
Bus Write operation. See the Status Register for
details on how to identify if the Program/Erase
Controller has started the Block Erase operation.
If any selected blocksare protected then these are
ignored and all the other selected blocks are
erased. If all of the selected blocks are protected
the Block Erase operation appears to start but will
terminate within about 100
μ
s, leaving the data un-
changed. No errorcondition is given when protect-
ed blocks are ignored.
During the Block Erase operation the memory will
ignore all commands except the Erase Suspend
and Read/Reset commands. Typical block erase
times are given in Table 9. All Bus Read opera-
tions during the Block Erase operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the Block Erase operation has completedthe
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read mode.
The Block Erase Command sets all of the bits in
the unprotected selected blocks to ’1’. All previous
data in the selected blocks is lost.
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| M29W400DB45ZE6E | 功能描述:閃存 4 MBIT 3V SUPPLY RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲(chǔ)類型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| M29W400DB45ZE6E_NUD | 制造商:Micron Technology Inc 功能描述: |
| M29W400DB45ZE6F | 制造商:Micron Technology Inc 功能描述:PARALLEL NOR - Tape and Reel |
| M29W400DB55N1 | 功能描述:閃存 512Kx8 or 256Kx16 55 RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲(chǔ)類型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| M29W400DB55N3T | 功能描述:IC FLASH 4MBIT 55NS 48TSOP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:Axcell™ 產(chǎn)品變化通告:Product Discontinuation 26/Apr/2010 標(biāo)準(zhǔn)包裝:136 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 同步，DDR II 存儲(chǔ)容量:18M（1M x 18） 速度:200MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.9 V 工作溫度:0°C ~ 70°C 封裝/外殼:165-TBGA 供應(yīng)商設(shè)備封裝:165-CABGA（13x15） 包裝:托盤 其它名稱:71P71804S200BQ |
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