- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359049 > M29W640DB90ZA1E (意法半導(dǎo)體) 64 Mbit 8Mb x8 or 4Mb x16, Boot Block 3V Supply Flash Memory PDF資料下載
參數(shù)資料
| 型號(hào)： | M29W640DB90ZA1E |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 64 Mbit 8Mb x8 or 4Mb x16, Boot Block 3V Supply Flash Memory |
| 中文描述： | 64兆位和8Mb x8或4Mb的x16插槽，啟動(dòng)塊3V電源快閃記憶體 |
| 文件頁(yè)數(shù)： | 8/49頁(yè) |
| 文件大?。?/td> | 945K |
| 代理商： | M29W640DB90ZA1E |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)當(dāng)前第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)
M29W640DT, M29W640DB
8/49
SIGNAL DESCRIPTIONS
See
Figure 2., Logic Diagram
, and
Table
1., Signal Names
, for a brief overview of the sig-
nals connected to this device.
Address Inputs (A0-A21).
The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the Program/Erase Con-
troller.
Data Inputs/Outputs (DQ0-DQ7).
The Data I/O
outputs the data stored at the selected address
during a Bus Read operation. During Bus Write
operations they represent the commands sent to
the Command Interface of the Program/Erase
Controller.
Data Inputs/Outputs (DQ8-DQ14).
The Data I/O
outputs the data stored at the selected address
during a Bus Read operation when BYTE is High,
V
IH
. When BYTE is Low, V
IL
, these pins are not
used and are high impedance. During Bus Write
operations the Command Register does not use
these bits. When reading the Status Register
these bits should be ignored.
Data Input/Output or Address Input (DQ15A–1).
When BYTE is High, V
IH
, this pin behaves as a
Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, V
IL
, this pin behaves as an address
pin; DQ15A–1 Low will select the LSB of the ad-
dressed Word, DQ15A–1 High will select the MSB.
Throughout the text consider references to the
Data Input/Output to include this pin when BYTE is
High and references to the Address Inputs to in-
clude this pin when BYTE is Low except when
stated explicitly otherwise.
Chip Enable (E).
The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
High, V
IH
, all other pins are ignored.
Output Enable (G).
The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W).
The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
V
PP/
Write Protect (V
PP
/WP).
The
Protect
pin provides two functions. The V
PP
func-
tion allows the memory to use an external high
voltage power supply to reduce the time required
for Unlock Bypass Program operations. The
Write Protect function provides a hardware meth-
od of protecting the two outermost boot blocks.
The V
PP
/Write Protect pin must not be left floating
or unconnected.
When V
PP
/Write Protect is Low, V
IL
, the memory
protects the two outermost boot blocks; Program
V
PP
/Write
and Erase operations in this block are ignored
while V
PP
/Write Protect is Low.
When V
PP
/Write Protect
is High, V
IH
, the memory
reverts to the previous protection status of the two
outermost boot blocks. Program and Erase opera-
tions can now modify the data in the two outermost
boot blocks unless the block is protected using
Block Protection.
When V
PP
/Write Protect is raised to V
PP
the mem-
ory automatically enters the Unlock Bypass mode.
When V
PP
/Write Protect returns to V
IH
or V
IL
nor-
mal operation resumes. During Unlock Bypass
Program operations the memory draws I
PP
from
the pin to supply the programming circuits. See the
description of the Unlock Bypass command in the
Command Interface section. The transitions from
V
IH
to V
PP
and from V
PP
to V
IH
must be slower
than t
VHVPP
, see
Figure 13.
.
Never raise V
PP
/Write Protect to V
PP
from any
mode except Read mode, otherwise the memory
may be left in an indeterminate state.
A 0.1μF capacitor should be connected between
the V
PP
/Write Protect pin and the V
SS
Ground pin
to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during Unlock Bypass
Program, I
PP
.
Reset/Block Temporary Unprotect (RP).
The
Reset/Block Temporary Unprotect pin can be
used to apply a Hardware Reset to the memory or
to temporarily unprotect all Blocks that have been
protected.
Note that if V
PP
/WP is at V
IL
, then the two outer-
most boot blocks will remain protected even if RP
is at V
ID
.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V
IL
, for at least
t
PLPX
. After Reset/Block Temporary Unprotect
goes High, V
IH
, the memory will be ready for Bus
Read and Bus Write operations after t
PHEL
or
t
RHEL
, whichever occurs last. See the Ready/Busy
Output section,
Table 15.
and
Figure 12., Reset/
Block Temporary Unprotect AC Waveforms
, for
more details.
Holding RP at V
ID
will temporarily unprotect the
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from V
IH
to V
ID
must be slower than
t
PHPHH
.
Ready/Busy Output (RB).
The Ready/Busy pin
is an open-drain output that can be used to identify
when the device is performing a Program or Erase
operation. During Program or Erase operations
Ready/Busy is Low, V
OL
. Ready/Busy is high-im-
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M29W640DB | 64 Mbit 8Mb x8 or 4Mb x16, Boot Block 3V Supply Flash Memory |
| M29W640DB70N1E | 64 Mbit 8Mb x8 or 4Mb x16, Boot Block 3V Supply Flash Memory |
| M29W640DB70N1F | 64 Mbit 8Mb x8 or 4Mb x16, Boot Block 3V Supply Flash Memory |
| M29W640DB70N1T | 64 Mbit 8Mb x8 or 4Mb x16, Boot Block 3V Supply Flash Memory |
| M29W640DB70N6E | 64 Mbit 8Mb x8 or 4Mb x16, Boot Block 3V Supply Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M29W640DB90ZA6 | 功能描述:閃存 8Mx8 or 4Mx16 90ns RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲(chǔ)類型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| M29W640DB90ZA6T | 制造商:Micron Technology Inc 功能描述:FLASH PARALLEL 3V/3.3V 64MBIT 8MX8/4MX16 90NS 63TFBGA - Tape and Reel |
| M29W640DT90N6 | 功能描述:閃存 8Mx8 or 4Mx16 90ns RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲(chǔ)類型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| M29W640DT90N6E | 功能描述:閃存 8Mx8 or 4Mx16 90ns RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲(chǔ)類型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| M29W640DT90ZA6 | 功能描述:閃存 8Mx8 or 4Mx16 90ns RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲(chǔ)類型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。