參數(shù)資料
型號: M29W640DT70N1E
廠商: 意法半導(dǎo)體
英文描述: Low-Power Single Inverter Buffer/Driver with Open-Drain Outputs 5-SC70 -40 to 85
中文描述: 64兆位和8Mb x8或4Mb的x16插槽,啟動塊3V電源快閃記憶體
文件頁數(shù): 48/49頁
文件大?。?/td> 945K
代理商: M29W640DT70N1E
M29W640DT, M29W640DB
48/49
REVISION HISTORY
Table 29. Document Revision History
Date
Version
Revision Details
14-Dec-2001
-01
Document released
19-Apr-2002
-02
Description of Ready/Busy signal clarified (and
Figure 12.
modified)
Clarified allowable commands during Block Erase
Clarified the mode the device returns to in the CFI Read Query command section
tPLYH (time to reset device) respecified. Correction to table of Commands.
24-Apr-2002
-03
Values for addresses 23h and 25h corrected in CFI Query System Interface Information
table in Appendix B
05-Sep-2002
3.1
When in Extended Block mode, the block at the boot block address can be used as OTP.
Value of electronic signature changed. Data Toggle Flow chart corrected. SO44 package
removed. Double Word Program Time (typ) changed to 20s. Revision numbering
modified: a minor revision will be indicated by incrementing the digit after the dot, and a
major revision, by incrementing the digit before the dot (revision version 03 equals 3.0).
08-Jan-2003
3.2
Values corrected for typical times for Double Word Program (Byte or Word) and Chip
Program (Quadruple Byte, Double Word) in the Program, Erase Times and Program,
Erase Endurance Cycles table.
Document promoted from Product Preview to Preliminary Data.
04-Apr-2003
3.3
Data Retention and Erase Suspend Latency Time parameters added to
Table
6., Program, Erase Times and Program, Erase Endurance Cycles
, and Typical after 100k
W/E Cycles column removed.
I
ID
(Identification) current removed from
Table 11., DC Characteristics
. Data modified at
addresses 2Eh, 31h, 32h in Table
24
.
Extended Memory Block Verify Codes modified in Tables
2
and
3
, “
Bus Operations, BYTE
= V
IL
” and “
Bus Operations, BYTE = V
IH
”, respectively. Block 75 address space corrected
for x8 mode in
Table 19., Top Boot Block Addresses, M29W640DT
, and Block 71
address space corrected for x8 mode in
Table 20., Bottom Boot Block Addresses,
M29W640DB
.
APPENDIX C., EXTENDED MEMORY BLOCK
, added. V
SS
pin connection to ground
clarified.
Lead-free package options E and F added to
Table 18., Ordering Information Scheme
.
2-Oct-2003
3.4
Status of Ready/Busy signal for Erase Suspend Operation modified in Table 7, Status
Register Bits.
Double Word Program Command modified in COMMAND INTERFACE section.
TLEAD parameter added in
Table 8., Absolute Maximum Ratings
.
Note modified and addresses 31h to 3Ch added in
Table 24., Device Geometry
Definition
.
Addresses 43h and 4Eh modified; addresses 4Fh and 50h added in
Table 25., Primary
Algorithm-Specific Extended Query Table
.
10-Nov-2003
3.5
70ns access time option removed.
19-Dec-2003
3.6
V
PP
and I
PP
test conditions updated in
Table 11., DC Characteristics
.
Block Protect/Unprotect code updated in
APPENDIX B.
,
Table 25.
.
Customer Lockable Extended Block mechanism modified in
APPENDIX C., EXTENDED
MEMORY BLOCK
.
APPENDIX D., BLOCK PROTECTION
updated: Note 1 added in the In-System
Technique section and Note 2 added below
Figure 18., In-System Equipment Group
Protect Flowchart
.
10-Dec-2004
5.0
Document status updated to Full Datasheet.
Status of Ready/Busy signal for Program Error, Chip Erase and Block Erase modified in
Table 7., Status Register Bits
.
相關(guān)PDF資料
PDF描述
M29W640DT70N1F Low-Power Single Inverter Buffer/Driver with Open-Drain Outputs 5-SC70 -40 to 85
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M29W640DT70N6E Low-Power Single Inverter Buffer/Driver with Open-Drain Outputs 5-SC70 -40 to 85
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