參數(shù)資料
型號: M29W800AT120M1T
廠商: 意法半導(dǎo)體
英文描述: Low-Power Single Schmitt-Trigger Buffer 5-DSBGA -40 to 85
中文描述: 8兆1兆x8或512KB的x16插槽,引導(dǎo)塊低壓單電源閃存
文件頁數(shù): 17/33頁
文件大?。?/td> 234K
代理商: M29W800AT120M1T
17/33
M29W800AT, M29W800AB
Table 17. Write AC Characteristics, W Controlled
(T
A
= 0 to 70
°
C, –20 to 85
°
C or –40 to 85
°
C)
Note: 1. Sampled only, not 100% tested.
2. This timing is for Temporary Block Unprotection operation.
Symbol
Alt
Parameter
M29W800AT / M29W800AB
Unit
80
90
V
CC
= 3.0V to 3.6V
CL = 30pF
V
CC
= 3.0V to 3.6V
CL = 30pF
Min
Max
Min
Max
t
AVAV
t
WC
Address Valid to Next Address Valid
80
90
ns
t
AVWL
t
AS
Address Valid to Write Enable Low
0
0
ns
t
DVWH
t
DS
Input Valid to Write Enable High
35
45
ns
t
ELWL
t
CS
Chip Enable Low to Write Enable Low
0
0
ns
t
GHWL
Output Enable High to Write Enable Low
0
0
ns
t
PHPHH(1, 2)
t
VIDR
RP Rise Time to V
ID
500
500
ns
t
PHWL(1)
t
RSP
RP High to Write Enable Low
4
4
μ
s
t
PLPX
t
RP
RP Pulse Width
500
500
ns
t
VCHEL
t
VCS
V
CC
High to Chip Enable Low
50
50
μ
s
t
WHDX
t
DH
Write Enable High to Input Transition
0
0
ns
t
WHEH
t
CH
Write Enable High to Chip Enable High
0
0
ns
t
WHGL
t
OEH
Write Enable High to Output Enable Low
0
0
ns
t
WHRL(1)
t
BUSY
Program Erase Valid to RB Delay
90
90
ns
t
WHWL
t
WPH
Write Enable High to Write Enable Low
30
30
ns
t
WLAX
t
AH
Write Enable Low to Address Transition
45
45
ns
t
WLWH
t
WP
Write Enable Low to Write Enable High
35
35
ns
Block Erase (BE) Instruction.
This
uses a minimum of six write cycles. The Erase
Set-up command 80h is written to address AAAh
in the Byte-wide configuration or address 555h in
the Word-wide configuration on third cycle after
the two Coded cycles. The Block Erase Confirm
command 30h is similarly written onthe sixth cycle
after anothertwo Coded cycles.During the input of
the second command an address within the block
to beerased is given and latched into the memory.
Additional block Erase Confirm commands and
block addresses can be written subsequently to
erase other blocks in parallel, without further Cod-
ed cycles. The erase will start after the erase tim-
eout period (seeErase TimerBit DQ3 description).
instruction
Thus, additionalErase Confirm commands for oth-
er blocksmust begiven within this delay. The input
of a new Erase Confirm command will restart the
timeout period. The status of the internal timer can
be monitoredthrough the level of DQ3, if DQ3 is ’0’
the Block Erase Command has been given and
the timeoutis running, if DQ3is ’1’, thetimeout has
expired and the P/E.C. is erasing the Block(s). If
the second command given is not an erase con-
firm or if the Coded cycles are wrong, the instruc-
tion aborts, and the device is reset to Read Array.
It is not necessary to program the block with 00h
as the P/E.C. will do this automatically before to
erasing to FFh. Read operations after the sixth ris-
ing edge of W orE output the status register status
bits.
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