參數(shù)資料
型號: M2V56S20TP
廠商: Mitsubishi Electric Corporation
英文描述: 256M Synchronous DRAM
中文描述: 256M同步DRAM
文件頁數(shù): 28/49頁
文件大小: 244K
代理商: M2V56S20TP
Feb.2000
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
256M Synchronous DRAM
28
DQM CONTROL
DQMU/L is a dual functional signal defined as the data mask for writes and the output disable for
reads. During writes, DQMU/L masks input data word by word. DQMU/L to Data In latency is 0.
During reads, DQMU/L forces output to Hi-Z word by word. DQMU/L to output Hi-Z latency is 2.
DQM Function
CLK
Command
DQ
DQMU/L
masked by DQMU/L=H
disabled by DQMU/L=H
Write
Read
D0
D2
D3
Q0
Q1
Q3
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