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deeopmen
Preliminary Specifications REV.E
Specifications in this manual are tentative and subject to change.
DMAC
Mitsubishi microcomputers
M30220 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
55
DMAC
This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent to
memory without using the CPU. DMAC shares the same data bus with the CPU. The DMAC is given a
higher right of using the bus than the CPU, which leads to working the cycle stealing method. On this
account, the operation from the occurrence of DMA transfer request signal to the completion of 1-word (16-
bit) or 1-byte (8-bit) data transfer can be performed at high speed. Figure 1.12.1 shows the block diagram
of the DMAC. Table 1.12.1 shows the DMAC specifications. Figures 1.12.2 to 1.12.4 show the registers
used by the DMAC.
Figure 1.12.1. Block diagram of DMAC
A
A
AA
AA
AA
AA
AA
AA
A
A
A
A
A
A
Data bus low-order bits
AA
DMA latch low-order bits
DMA0 source pointer SAR0(20)
AA
AA
DMA0 destination pointer DAR0 (20)
AA
DMA0 forward address pointer (20) (Note)
AA
Data bus high-order bits
AA
AA
AA
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Address bus
DMA1 destination pointer DAR1 (20)
AA
DMA1 source pointer SAR1 (20)
AA
DMA1 forward address pointer (20) (Note)
AA
DMA0 transfer counter reload register TCR0 (16)
A
(addresses 0029
16
, 0028
16
)
AA
DMA0 transfer counter TCR0 (16)
AA
A
AA
A
DMA1 transfer counter TCR1 (16)
(addresses 0039
16
, 0038
16
)
(addresses 0022
16
to 0020
16
)
16
to 0024
16
)
(addresses 0032
16
to 0030
16
)
(addresses 0036
16
to 0034
16
)
Note: Pointer is incremented by a DMA request.
AA
Either a write signal to the software DMA request bit or an interrupt request signal is used as a DMA transfer
request signal. But the DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the
interrupt priority level. The DMA transfer doesn't affect any interrupts either.
If the DMAC is active (the DMA enable bit is set to 1), data transfer starts every time a DMA transfer request
signal occurs. If the cycle of the occurrences of DMA transfer request signals is higher than the DMA
transfer cycle, there can be instances in which the number of transfer requests doesn't agree with the
number of transfers. For details, see the description of the DMA request bit.