參數(shù)資料
型號(hào)： M30260F3TGP-U7
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP48
封裝： 7 X 7 MM, 0.50 MM PITCH, LEAD FREE, PLASTIC, LQFP-48
文件頁(yè)數(shù)： 17/26頁(yè)
文件大?。?/td> 185K
代理商： M30260F3TGP-U7
M16C/26A Group (M16C/26A, M16C/26T)
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
6. Functional differences
Rev.0.40 2004.07.30
page 24 of 24
REJ03B0071-0040Z
Item
M16C/26A
M16C/26
Clock Generation
4 circuits (Main clock oscillation circuit,
3 circuits (Main clock oscillation circuit,
Circuit
Sub clock oscillation circuit,
On-chip oscillator,
On-chip oscillator)
PLL frequency synthesizer)
System Clock
On-chip oscillator
Main clock
Source After Reset
(Initial value "1" of CM21 bit)
(Initial value "0" of CM21 bit)
(Initial value of the CM21
bit in the CM2 register)
Internal RAM Retention Available
Not available
limit Detection Circuit
(VC25 bit)
(Reserved bit)
(The b5 bit in the VCR2 register)
On-chip Oscillator Clock
Selectable (8MHz/1MHz/500KHz)
Fixed (1MHz)
PACR2 to PACR0 in Necessary to set after reset
No PACR register
the PACR Register
48pin:"1002", 42pin:"0012"
IFSR20 Bit in the
Necessary to set to "1" after reset
No IFSR2A register
IFSR2A Register
External Interrupt
8 causes (INT2 added)
7 causes
13 pin (48-pin version)
________ _____
INT2/ZP
IVCC
Function
P70, P71
N-ch open drain output and CMOS
N-ch open drain output
output are selectable by S/W
A/D Input Pin
12 channels
8 channels
(48-pin version)
A/D Operation Mode 8 modes (single, repeat, single sweep,
5 modes (single, repeat, single sweep,
repeat sweep mode 0, repeat sweep
mode 1, simultaneous sampling,
mode 1)
delayed trigger mode 0, delayed
trigger mode 1)
1 shunt current measurement function
is available
Timer B Operation
5 modes (timer, event counter, pulse
4 modes (timer, event counter, pulse
Mode
periods measurement, pulse width
measurment, A/D trigger)
measurment)
1 shunt current measurement function
is available
CRC Calculation
Available (compatible to CRC-CCITT
Not available
and CRC-16 methods)
Three-Phase Motor
Waveform output/Switching port output Waveform output/Switching port output
Control
by software is enabled
by software is disabled
Position-data-retain function
No position-data-retain function
Digital Debounce
_______ _____
This function is in the NMI/SD pin and
Not available
Function
________
INT5 pin
3 pin (48-pin version)
P90/CLKOUT/TB0IN/AN30
P90/TB0IN
Function
(CLKOUT: f1, f8, f32, and fC output)
UART1 Compatible
Switching to P64 to P67 or P70 to P73
P64 to P67
Pin
is enabled
Flash Memory
Protection to blocks 0, 1 by FMR02 bit
Protection to blocks 0,1 by FMR02 bit
Protect Function
Protection to the blocks 0 to 3 by
FMR16 bit
Package
48P6Q, 42P2R
48P6Q
6.2 Functional differences between M16C/26A and M16C/26
Note. Since the emulator between the M16C/26A and M16C/29 group are same, all functions of M16C/29
are built in the emulator. When evaluating M16C/26A group, do not access to the SFR which is not
built in M16C/26A group.
Refer to Hardware Manual about detail and electrical characteristics.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M30260F6AGP D3 制造商:Renesas Electronics Corporation 功能描述:
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