- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45015 > M30302GGPFP 16-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PQFP100 PDF資料下載
參數(shù)資料
| 型號： | M30302GGPFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, LEAD FREE, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 42/57頁 |
| 文件大?。?/td> | 649K |
| 代理商： | M30302GGPFP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁當前第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁
5. Electrical Characteristics
Page 47 of 53
VCC1=VCC2=3V
Switching Characteristics
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr =
20 to 85°C / 40 to 85°C unless otherwise specified)
NOTES:
1.
Calculated according to the BCLK frequency as follows:
n is “1” for 1-wait setting, f(BCLK) is 12.5MHz or less.
2.
Calculated according to the BCLK frequency as follows:
3.
This standard value shows the timing when the output is off, and
does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t =
CR X ln (1VOL / VCC1)
by a circuit of the right figure.
For example, when VOL = 0.2VCC1, C = 30pF, R = 1k
Ω, hold time
of output ”L” level is
t =
30pF X 1kΩ X In(10.2VCC1 / VCC1)
= 6.7ns.
Table 5.44
Memory Expansion and Microprocessor Modes (for 1 wait setting and external area
access)
Symbol
Parameter
Standard
Unit
Min.
Max.
td(BCLK-AD)
Address Output Delay Time
See
30
ns
th(BCLK-AD)
Address Output Hold Time (in relation to BCLK)
0
ns
th(RD-AD)
Address Output Hold Time (in relation to RD)
0
ns
th(WR-AD)
Address Output Hold Time (in relation to WR)
ns
td(BCLK-CS)
Chip Select Output Delay Time
30
ns
th(BCLK-CS)
Chip Select Output Hold Time (in relation to BCLK)
0
ns
td(BCLK-ALE)
ALE Signal Output Delay Time
25
ns
th(BCLK-ALE)
ALE Signal Output Hold Time
-4
ns
td(BCLK-RD)
RD Signal Output Delay Time
30
ns
th(BCLK-RD)
RD Signal Output Hold Time
0
ns
td(BCLK-WR)
WR Signal Output Delay Time
30
ns
th(BCLK-WR)
WR Signal Output Hold Time
0
ns
td(BCLK-DB)
Data Output Delay Time (in relation to BCLK)
40
ns
th(BCLK-DB)
Data Output Hold Time (in relation to BCLK) (3)
4ns
td(DB-WR)
Data Output Delay Time (in relation to WR)
ns
th(WR-DB)
Data Output Hold Time (in relation to WR)(3)
ns
td(BCLK-HLDA)
HLDA Output Delay Time
40
ns
n0.5
–
()x10
9
fBCLK
()
------------------------------------
40 ns
[]
–
0.5x10
9
fBCLK
()
------------------------10 ns
[]
–
DBi
R
C
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M30302SPFP | 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP100 |
| M30302GDP-XXXFP | 16-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PQFP100 |
| M30302GEP-XXXGP | 16-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PQFP100 |
| M30304GDPGP | 16-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PQFP100 |
| M30302FCPGP | 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP100 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M30302GGPGP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30302GGP-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30302GGP-XXXGP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30302M4-XXX | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30302M4-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。