參數(shù)資料
型號: M30302M8L-XXXFP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 20 MM, PLASTIC, QFP-100
文件頁數(shù): 20/165頁
文件大?。?/td> 2188K
代理商: M30302M8L-XXXFP
Clock asynchronous serial I/O (UART) mode
116
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(b) Function for switching serial data logic (UART2)
When the data logic select bit (bit 6 of address 037D16) is assigned “1”, data is inverted in writing to the
transmission buffer register or reading the reception buffer register. Figure 1.16.20 shows the ex-
ample of timing for switching serial data logic.
Figure 1.16.20. Timing for switching serial data logic
ST : Start bit
P : Even parity
SP : Stop bit
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
SP
ST
D3
D4
D5
D6
D7
P
D0
D1
D2
Transfer clock
TxD2
(no reverse)
TxD2
(reverse)
“H”
“L”
“H”
“L”
“H”
“L”
When LSB first, parity enabled, one stop bit
Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
Figure 1.16.19. Typical receive timing in UART mode
(a) Sleep mode (UART0, UART1)
This mode is used to transfer data between specific microcomputers among multiple microcomputers
connected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses
03A016, 03A816) is set to “1” during reception. In this mode, the unit performs receive operation when
the MSB of the received data = “1” and does not perform receive operation when the MSB = “0”.
D0
Start bit
Sampled “L”
Receive data taken in
BRGi count
source
Receive enable bit
RxDi
Transfer clock
Receive
complete flag
RTSi
Stop bit
“1”
“0”
“1”
“H”
“L”
The above timing applies to the following settings :
Parity is disabled.
One stop bit.
RTS function is selected.
Receive interrupt
request bit
“0”
“1”
Transferred from UARTi receive register to
UARTi receive buffer register
Reception triggered when transfer clock
is generated by falling edge of start bit
D7
D1
Cleared to “0” when interrupt request is accepted, or cleared by software
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