參數(shù)資料
型號: M30302MA-XXXGP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, PLASTIC, QFP-100
文件頁數(shù): 69/177頁
文件大小: 2355K
代理商: M30302MA-XXXGP
Timing (Vcc = 5V)
160
Mitsubishi microcomputers
M16C / 30 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory Expansion Mode and Microprocessor Mode
(When accessing external memory area with wait, and select multiplexed bus)
BCLK
CSi
ALE
RD
4ns.min
tcyc
ADi
BHE
ADi
/DBi
td(AD–ALE)
Read timing
0ns.min
BCLK
CSi
ALE
–4ns.min
4ns.min
tcyc
ADi
BHE
ADi
/DBi
Write timing
Address
Measuring conditions :
VCC=5V
Input timing voltage : Determined with VIL=0.8V, VIH=2.5V
Output timing voltage : Determined with VOL=0.8V, VOH=2.0V
(tcyc/2)ns.min
Address
Data input
(tcyc/2)ns.min
td(BCLK–ALE)
(tcyc/2)ns.min
th(WR–CS)
Address
(tcyc x 3/2–40)ns.min
td(BCLK–ALE)
(tcyc/2)ns.min
(tcyc/2-25)ns.min
Address
25ns.max
tSU(DB–RD)
tac3(RD–DB)
(tcyc/2)ns.min
th(ALE–AD)
30ns.min
td(AD–RD)
0ns.min
tdz(RD–AD)
8ns.max
td(AD–WR)
0ns.min
Data output
WR,WRL,
WRH
td(BCLK–CS)
25ns.max
th(RD–CS)
th(BCLK–CS)
4ns.min
th(BCLK–AD)
th(RD–DB)
0ns.min
40ns.min
25ns.max
td(BCLK–AD)
–4ns.min
th(BCLK–ALE)
td(BCLK–RD)
25ns.max
th(RD–AD)
th(BCLK–RD)
0ns.min
td(BCLK–CS)
25ns.max
th(BCLK–CS)
th(BCLK–DB)
4ns.min
th(WR–DB)
td(DB–WR)
th(BCLK–AD)
td(AD–ALE)
(tcyc/2–25)ns.min
td(BCLK–AD)
25ns.max
th(BCLK–ALE)
25ns.max
td(BCLK–WR)
th(BCLK–WR)
th(WR–AD)
td(BCLK–DB)
40ns.max
VCC = 5V
Figure 1.23.6. VCC = 5V timing diagram (5)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M30302MC 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M30302MCL-XXX 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
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M30302MCL-XXXGP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M30302MCP-XXX 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER