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參數(shù)資料
| 型號： | M30612MA-310FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | MICA RoHS Compliant: No |
| 中文描述： | 單片16位CMOS微機(jī) |
| 文件頁數(shù)： | 36/197頁 |
| 文件大?。?/td> | 2673K |
| 代理商： | M30612MA-310FP |
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Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Status Transition Of BCLK
36
0
1
1
0
0
0
0
0
0
1
1
0
0
1
0
0
0
0
0
0
0
0
1
Invalid
Invalid
Invalid
Invalid
Invalid
1
1
Division by 2 mode
Division by 4 mode
Division by 8 mode
Division by 16 mode
No-division mode
Low-speed mode
Low power dissipation mode
Invalid
1
0
Invalid
Invalid
Invalid
1
0
Invalid
Invalid
Invalid
Invalid
Status Transition Of BCLK
Power dissipation can be reduced and low-voltage operation achieved by changing the count source for
BCLK. Table 1.13.4 shows the operating modes corresponding to the settings of system clock control
registers 0 and 1.
When reset, the device starts in division by 8 mode. The main clock division select bit 0(bit 6 at address
0006
16
) changes to “1” when shifting from high-speed/medium-speed to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
The following shows the operational modes of BCLK.
(1) Division by 2 mode
The main clock is divided by 2 to obtain the BCLK.
(2) Division by 4 mode
The main clock is divided by 4 to obtain the BCLK.
(3) Division by 8 mode
The main clock is divided by 8 to obtain the BCLK. When reset, the device starts operating from this
mode. Before the user can go from this mode to no division mode, division by 2 mode, or division by 4
mode, the main clock must be oscillating stably. When going to low-speed or lower power consumption
mode, make sure the sub-clock is oscillating stably.
(4) Division by 16 mode
The main clock is divided by 16 to obtain the BCLK.
(5) No-division mode
The main clock is divided by 1 to obtain the BCLK.
(6) Low-speed mode
f
C
is used as the BCLK. Note that oscillation of both the main and sub-clocks must have stabilized before
transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the sub-
clock starts. Therefore, the program must be written to wait until this clock has stabilized immediately
after powering up and after stop mode is cancelled.
(7) Low power dissipation mode
f
C
is the BCLK and the main clock is stopped.
Note : Before the count source for BCLK can be changed from X
IN
to X
CIN
or vice versa, the clock to which
the count source is going to be switched must be oscillating stably. Allow a wait time in software for
the oscillation to stabilize before switching over the clock.
CM17
CM16
CM07
CM06
CM05
CM04
Operating mode of BCLK
Table 1.12.4. Operating modes dictated by settings of system clock control registers 0 and 1
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