參數(shù)資料
型號: M30622F8PGP#U3
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 17/101頁
文件大小: 1126K
代理商: M30622F8PGP#U3
1. Overview
Page 22 of 96
Figure 1.9
Pin Configuration (Top View)
44
45
46
47
48
49
50
51
52
53
54
55
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
56
P4
_2
P3_
0
P3
_1
P3
_2
P3
_3
P3
_4
P3
_5
P3
_6
P3
_7
P4
_0
P4
_1
P0_0/AN0_0
P0_1/AN0_1
P0_2/AN0_2
P0_3/AN0_3
P0_4/AN0_4
P0_5/AN0_5
P0_6/AN0_6
P0
_7/AN
0_7
P10_1/AN1
P10_2/AN2
P10_3/AN3
P10_4/AN4/KI0
P10_5/AN5/KI1
P10_6/AN6/KI2
P10_7/AN7/KI3
P2
_0
/A
N
2
_
0
P2
_1
/A
N
2
_
1
P2
_2
/A
N
2
_
2
P2
_4
/A
N
2
_
4
P2
_5
/A
N
2
_
5
P2
_6/AN
2_6
P2
_7
/A
N
2
_
7
P2
_3/AN
2_3
M16C/62P Group
(M16C/62P, M16C/62PT)
Package : PRQP0080JA-A (80P6S-A)
NOTES:
1. P7_0 and P7_1 are N channel open-drain output pins.
PIN CONFIGURATION (top view)
1
2
3
4
5
6
7
8
9 10 11 12 13 141516 17
75
76
77
78
79
80
VC
C
1
XI
N
XO
UT
VS
S
R
ESET
C
N
VSS(
BYTE)
P
8_7
/X
C
IN
P
8
_6
/X
CO
UT
P9_
3
/D
A
0/
T
B
3I
N
P
9
_4/
D
A
1/TB
4
IN
P
9
_
5
/A
N
E
X
0
/C
L
K
4
P8
_2
/I
N
T
0
P8
_3
/I
N
T
1
P
8_1/TA
4
IN
P
8_4
/I
N
T
2/
ZP
P8
_0
/T
A
4
O
U
T
P8
_5
/N
M
I
VREF
AVSS
AVCC
P10_0/AN0
P9_6/ANEX1/SOUT4
P
9
_
0
/T
B
0
IN
/C
L
K
3
P9_7/ADTRG/SIN4
P9_
2
/TB
2I
N/
SO
UT
3
18 19 20
21
22
23
24
25
26
P6_5/CLK1
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1
P7_1/RXD2/SCL2/TA0IN/TB5IN (1)
P7_0/TXD2/SDA2/TA0OUT (1)
P7_6/TA3OUT
P
7_7
/T
A
3
IN
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
P4_3
P5_6
P5_5
P5_4
P5_3
P5_2
P5_7/CLKOUT
P6_3/TXD0/SDA0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_0/CTS0/RTS0
P6_4/CTS1/RTS1/CTS0/CLKS1
P5_0
P5_1
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