Clock asynchronous serial I/O (UART) mode
Mitsubishi microcomputers
M16C / 62 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
135
(c) Function for switching serial data logic (UART2)
When the data logic select bit (bit 6 of address 037D
16
) is assigned 1, data is inverted in writing to the
transmission buffer register or reading the reception buffer register. Figure 1.19.20 shows the ex-
ample of timing for switching serial data logic.
Figure 1.19.20. Timing for switching serial data logic
ST : Start bit
P : Even parity
SP : Stop bit
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
SP
ST
D3
D4
D5
D6
D7
P
D0
D1
D2
Transfer clock
TxD
2
(no reverse)
TxD
2
(reverse)
“H”
“L”
“H”
“L”
“H”
“L”
When LSB first, parity enabled, one stop bit
(d) TxD, RxD I/O polarity reverse function (UART2)
This function is to reverse T
X
D pin output and R
X
D pin input. The level of any data to be input or output
(including the start bit, stop bit(s), and parity bit) is reversed. Set this function to “0” (not to reverse) for
usual use.
(e) Bus collision detection function (UART2)
This function is to sample the output level of the T
X
D pin and the input level of the R
X
D pin at the rising
edge of the transfer clock; if their values are different, then an interrupt request occurs. Figure 1.19.21
shows the example of detection timing of a buss collision (in UART mode).
Figure 1.19.21. Detection timing of a bus collision (in UART mode)
ST : Start bit
SP : Stop bit
ST
ST
SP
SP
Transfer clock
TxD
2
RxD
2
Bus collision detection
interrupt request signal
“H”
“L”
“H”
“L”
“H”
“L”
“1”
“0”
Bus collision detection
interrupt request bit
“1”
“0”